Simulations for thermal warpage and pressure nonlinearity of monolithic CMOS pressure sensors

The operation function of a piezoresistive pressure sensor utilizes a voltage output to detect the magnitude of pressure. The basic design concept for monolithic pressure sensors is to fabricate a standard submicron CMOS process with appropriate modifications to integrate on-chip signal conditioning circuits with anisotropic-etched piezoresistive sensing elements. In this study, thermal stress simulations with applied pressure loadings are used to estimate the electromechanical behavior of a new monolithic sensing element concept design. The major tasks are to predict the ripple deformation of a silicon diaphragm due to the thermal residual stresses from multiple passivation layers and estimate the pressure nonlinearities on the transducer. More detailed approaches with design and performance concerns are also discussed.     

Integrated test chips improve IC assembly

The use of test dies integrated with a semiconductor wafer to gauge environmental stresses effectively during the packaging and processing phases is discussed. These special-purpose assembly test chips (ATCs) are designed primarily for studying failures of the package-centered and composite types. These chips usually provide a way to stress the die, and they include transducers for monitoring the die's response to the stress. A variety of structures has been used to measure parameters associated with package-related failures. Corrosion detectors, moisture detectors, mechanical stress sensors, mobile ion sensors, thermal resistance measurement circuits, and multifunction test chips are examined     

基于复合介质层材料的硅通孔热结构耦合分析

硅通孔(TSV)技术是三维封装的关键技术,对三维IC的可靠性起决定性作用。基于ANSYS Workbench平台,通过有限元仿真对退火阶段的TSV模型进行热结构耦合分析。比较了二氧化硅(SiO₂)介质层与苯并环丁烯(BCB)介质层在不同负载下的热应力,研究了不同填充材料、介质层厚度、通孔直径、深宽比条件下的热应力分布和热应力影响,分析了碳纳米管掺杂的苯并环丁烯(BCB-CNT)介质层的热应力。结果表明,该复合介质层能有效降低热应力,提高了三维IC的可靠性。     

Electromigration of silicon and phosphorus in tantalum polycide interconnections

TaSi2/n⁺-poly-Si interconnections of integrated circuits were investigated after high direct current density stress at elevated temperatures. The current density was increased up to values that caused failures of the interconnections due to electromigration. We found in our experiments that material migrated from the anode to the cathode causing open-circuit failure at the anode region. At the cathode, the material piled up forming hillocks. Material depletion and accumulation are caused by positive or negative mass flow divergences due to temperature gradients near the pads. The accumulated material at the cathode was analyzed by high-resolution Auger and SIMS spectroscopy. The obtained spectra show only silicon and phosphorus peaks with an increased phosphorus concentration at the cathode area. Hence, it can be concluded that in TaSi2/n⁺-poly-Si interconnection mainly material of the polysilicon layer including the dopant phosphorus is moved by electromigration. In contrast to these results of dc experiments, no electromigration occurred during equivalent ac stress.     

PBGA器件固化残余应力的有限元分析

采用有限元分析软件模拟研究了PBGA器件在先固化再进行温度加载和直接从温度循环开始加载两种情况下,固化过程对 PBGA 器件的影响,发现固化过程不仅改变了器件中芯片的应力分布,而且劣化了 DA(环氧树脂)材料与芯片接触面的应力值,也同时使得 BT 材料基底中的应力分布产生较大的改变。并且对 DA 材料选用几种不同的固化时间,发现固化时间的不同对器件封装残余应力的大小和最大应力位置有重要的影响,这为预测芯片的垂直开裂的位置提供了很好的依据。     

Dislocation dynamics in heterojunction bipolar transistor under current induced thermal stress

Dislocation generation and multiplication in heterojunction bipolar transistors (HBTs) under electrical bias was studied using a finite element model. This model was developed to solve a physical viscoplastic solid mechanics problem using a time-dependent constitutive equation relating the dislocation dynamics to plastic deformation. The dislocations in HBTs are generated by the excessive stresses including thermal stress generated by the temperature change in the device during operation. It was found that the dislocation generation rate at the early stage and the stationary dislocation densities depend strongly on the current density.     

Influence of local thermal dissipation on electromigration in an Al thin-film line

To improve the reliability of Al thin-film lines in integrated circuits, the influence of local thermal dissipation on electromigration (EM) was investigated. By performing current stressing experiments on Al thin-film lines with a special design, the unique distribution of hillocks/voids around four representative zones was found. The underlying mechanism was explained by investigating the corresponding atomic flux divergence according to finite element analyses. Such unique distribution of hillocks/voids, differing from the general EM phenomenon with hillocks at anode and voids at cathode, indicates the influence of local thermal dissipation induced by the voltage-measuring pads. Moreover, by changing the position of the voltage-measuring pads in the Al thin-film line, it was found that when the position of local thermal dissipation is farther from the center of the line, the EM resistance is higher. This finding provides a valuable insight for improving the EM resistance of Al thin-film lines and therefore enhancing the reliability of the corresponding devices.     

In Situ Measurement of Stress and Whisker/Hillock Density During Thermal Cycling of Sn Layers

Compressive stress is believed to be the primary driving force that makes Sn whiskers/hillocks grow, but the mechanisms that create the stress (e.g., intermetallic compound growth) are difficult to control. As an alternative, the thermal expansion mismatch between the Sn layer and the substrate can be used to induce stress in a controlled way via heating and cooling. In this work, we describe real-time experiments which quantify the whiskering behavior and stress evolution during cyclic heating. The density of whiskers/hillocks is measured with an optical microscope, while the stress is measured simultaneously with a wafer-curvature-based multi-beam optical stress sensor. Results from three thermal cycles are described in which the samples are heated from room temperature to 65 °C at rates of 10, 30, and 240 °C/h. In each case, we find that the whisker/hillock formation is the primary source of stress relaxation. At fast heating rates, the relaxation is proportional to the number of hillocks, indicating that the stress is relaxed by the nucleation of many small surface features. At slower heating rates, the whisker/hillock density is lower, and continual growth of the features is suggested after nucleation. Long whiskers are found to be more likely to form in the slow heating cycle.     

Integrated transient thermal and mechanical analysis of molded PBGApackages during thermal shock

During thermal shock, large thermal gradients exist within a molded plastic ball grid array (PBGA) package. The conventional assumption of uniform temperature distribution becomes invalid. In this paper, an integrated thermal-mechanical analysis was performed to evaluate the transient effect of thermal shock. For comparison, an isothermal analysis was also conducted. The computational fluid dynamics (CFD) method was used to obtain the thermal boundary conditions surrounding the package. The heat transfer coefficient obtained through CFD was compared to two analytical solutions. It was found that the analytical values were not acceptable in the time period of interest. Therefore, to obtain the actual maximum die stress, CFD solution has to be used instead of analytical solutions to derive the thermal boundary condition. This boundary condition was then applied to the package and a sequentially coupled heat transfer and thermal stress analysis was performed. The transient analysis has shown that high stresses occur in the die due to thermal shock, which can not be seen under the traditional isothermal assumption. The impact of plastic ball grid array (PBGA) package parameters on transient die stress was also studied, including mold thickness and substrate thickness. The results in this paper could be applied to either wire bond or flip-chip PBGA packages     

The effect of grain orientation on the relaxation of thermomechanical stress and hillock growth in AI-1%Si conductor layers on silicon substrates

Hillocks are formed sporadically in Al-l%Si sputter layers on SiO₂/Si substrates during heat treatments in the range from 200 to 500°C. The driving force is the relaxation of thermomechanical stress in the grains induced by the thermal expansion mismatch between the metallization layer and the substrate. The orientations of individual grains and hillocks are measured on-line with a medium voltage transmission electron microscope by the Kikuchi pattern method. Thermomechanical stress in the grains is calculated with a biaxial strain model, considering the glide systems of dislocations for the individual grain orientations. In general, hillocks deviate from the ordinary 〈111〉 fiber texture of aluminum sputter layers. The spatial distribution of grain orientations is illustrated by orientation images using Miller indices or Rodrigues vectors.     

Plastic deformation and interfacial sliding in Al and Cu thin film: Si substrate systems due to thermal cycling

As a result of the large difference in thermal expansion coefficients between metal and Si, high stresses can develop in thin metallic films attached to Si substrates in microelectronic devices during thermal excursions experienced in processing steps or during usage. These stresses may induce plastic deformation of the thin films accompanied by creep and interfacial sliding, and have a pronounced effect on the reliability of microelectronic devices and components. Even though various methods have been proposed to study thermal stress, methodologies for studying plastic deformation of thin films are not well established. Here, we report the results of a study of plastic deformation and interfacial sliding of thin Al and Cu films on Si substrates during thermal cycling. Cross-sectional profiles of pattern-grown Al and Cu films of nominally 250 nm thickness were measured before and after thermal cycling by employing an atomic force microscope. Through statistical analysis, the size changes of the thin films induced by thermal cycling were determined. Finite element (FE) analyses were conducted to compute the stress and strain states within the thin film and at the interface, and the results were utilized to interpret the atomic force microscopy (AFM) observations. Experiments revealed that, following thermal cycling, Al films expanded relative to the Si substrate, whereas Cu films shrank, resulting in an alteration of the film-footprint on the substrate in both cases. Based on the FE calculations, this was attributed to net inelastic deformation of the thin films via creep and yielding, with the deformation being accommodated at the interface by diffusion-controlled interfacial sliding.     

Finite element analysis of thermal and mechanical stresses due to the grain anisotropy of polycrystalline β-Sn

In order to investigate the stress and strain distributions caused by the grain anisotropy of polycrystalline β-Sn, a finite-element (FE) analysis was conducted using a polycrystalline model that considers the effect of grain anisotropy on the elastic and plastic properties. Even in the case of thermal free expansion with a temperature change of 75 °C, plastic strains can be generated locally in polycrystalline β-Sn. This might be due to the high anisotropy of the thermal expansion coefficient and the low yield strength of β-Sn. It was found that both in-phase and out-of-phase thermal stresses can be present in the polycrystalline β-Sn simultaneously. The highest stress and strain appeared in the grains whose orientation is relatively different from those of neighboring grains, near the grain boundaries. This might cause the formation of a grain boundary void in the Pb-free solder. Comparing the strain distribution due to the thermal expansion coefficient anisotropy and the Young's modulus anisotropy, it was determined that the maximum value of the plastic strain due to the thermal expansion coefficient anisotropy is approximately 10% higher than that due to the anisotropy of Young's modulus, and the high strain areas are also different in the two cases. The thermo-mechanical fatigue life of β-Sn might be shorter than that estimated using the isothermal low cycle fatigue life at the same level as the macroscopic strain and could not be estimated by the previous method.     

An advanced finite element strategy for thermal stress field investigation in aluminium interconnections during processing of very large scale integration multilevel structures

An advanced strategy for modelling the thermal stress induced in aluminium interconnections during processing of multilevel structures is presented. The advantage of the approach described is that it allows the residual stresses from one processing step to be used as the initial conditions for a subsequent step. 2D elasto-plastic model (von Mises plastic criterion) is implemented in Finite Element Code and it is shown that even after significant relaxation by plastic deformation, high thermal stress resides in the aluminium line in both width and thickness directions. The technique demonstrated here is for a silicon-glass–aluminium-glass structure. However, it is readily extended to more complex situations and material combinations.     

Identifying electrical mechanisms responsible for functional failures during harsh external ESD and EMC aggression

For particular applications, system level stresses such as EMC stress or ESD (IEC61000-4-2) are directly applied to the integrated circuits with no external protections. Consequently, the integrated circuits have to be designed for reliability in order to stay alive but also to guarantee the normal operations during severe electrical aggressions. Unfortunately, the simulation of functional failures during severe ESD or EMC events remains very challenging for analog products due the frequency domain and to the high current injection mechanisms. This paper describes a test method to identify the design functions and the physical mechanisms that lead to functional failures when integrated circuits are submitted to system level stress.     

Finite element simulation of a stress history during themanufacturing process of thin film stacks in VLSI structures

High levels of interconnection line stress are a serious reliability problem for the integrated circuit industry. These stresses, which are due to the thermal expansion coefficient difference between the line and its surroundings, as well as to nonequilibrium film growth, can lead to failure mechanisms such as voiding and cracking. Historically, stresses in these lines have typically been modeled using a fixed configuration at the final process step. The stresses are calculated as the model Is cooled to room temperature. We have developed models to calculate stresses in interconnection structures as a function of process step, such as film deposition, etching, and thermal cycles. During processing both thermal and intrinsic stresses are induced, and continuously changed by subsequent process steps. This paper presents such an analysis of simple interconnection structures which contain two-level aluminum (Al) metal layers and a tungsten (W) via connection. Stress histories of the metal and via layers are obtained and discussed. This paper also discusses the effects on interconnection stress when intrinsic stresses in various layers are taken into account     

Thermo-mechanical stresses in copper interconnects - A modeling analysis

This study focuses on numerical modeling of thermo-mechanical stresses in copper interconnects. The three-dimensional analyses utilize a two-level metal structure connected by a via. Attention is devoted to the effects of the incorporation of polymer-based low-k dielectric material. Deformation is generated by thermal strain mismatches during cooling from an elevated temperature, as well as from cyclic thermal excursions. The thin barrier layers encasing the copper are also included in the models. Plastic deformation in the metal is taken into consideration in the analysis. The stress and deformation fields are examined in detail. It is found that the incorporation of low-k dielectric in place of traditional oxide-based dielectric significantly reduces the triaxial tensile stresses in copper but enhances plastic deformation, particularly in the via and its vicinity. The generation of shear stresses at the interface regions is also assessed. A parametric analysis is conducted to elucidate the individual influences of the thermal expansion and elastic properties of the dielectric material. Salient features having direct implications in device reliability are highlighted and discussed.     

Analysis of thermal stresses in copper interconnect/low-k dielectric structures

Numerical simulations of thermal stresses in copper (Cu) interconnect and low-k dielectric systems are carried out. The three-dimensional (3-D) finite-element analysis assumes a two-level metal structure connected by a via. Mechanical deformation is generated by thermal expansion mismatches during cooling and cyclic temperature changes. The thin barrier/etch stop layers, as well as oxide or polymer-based low-k dielectric materials, are all taken into account in the model. The stress and deformation fields are examined in detail; salient features having direct implications in device reliability are illustrated with representative contour plots. It is found that the use of low-k material in place of traditional oxide dielectric significantly reduces the triaxial tensile stresses in Cu but enhances plastic deformation, especially in the via region. The compliant low-k material causes the thin barrier layers to bear very high stresses. Deformation in the Cu line and via structure is more affected by the thermal expansion property of the dielectric, but the stresses in the barrier layers are more influenced by the elastic modulus of the dielectric.     

Plastic encapsulated components for cars

Thermal management in electronics packaging is important. Thermal stress greatly affects reliability and aging of electronic circuits. Our group developed a thermal simulation tool named TRESCOM for investigating thermal problems in electronic packaging. We used this tool for steady-state and dynamic analyses of the thermal qualities of PLCC and CLCC components. Our investigation demonstrated the surprising result that the thermal performance of the plastic encapsulated components is superior to hermetically sealed ceramic components. We conclude that plastic packages are reliable and can compete with ceramic packages at the elevated temperatures that are found in automotive applications     

Numerical investigation and experimental validation of residual stresses building up in microelectronics packaging

This paper comprises the numerical approach and the experimental validation technique developed to obtain the residual stresses building up during encapsulation process of integrated circuits. Residual stresses can be divided into cure and cooling induced parts. The curing originated stress had been mostly neglected in the literature and a special attention had always been given to detection of the thermal induced stress. In this study, both of the residual stresses, evolving during packaging, were investigated independently. The material behavior of the epoxy molding compound, EMC, was determined by the series of characterization experiments. The volumetric behavior of the EMC was investigated using PVT analysis, in which the total cure shrinkage of an initially uncured sample and the coefficient of thermal expansion of the same sample after full conversion were determined. The cure kinetics was studied using differential scanning calorimetry, DSC. The dynamic mechanical behavior was examined by dynamic mechanical analysis, DMA, at a fixed frequency. Besides, the time dependent behavior of the EMC was also determined by implementing the time–temperature superposition, TTS, test set-up in DMA. The shift factor was modeled using the combination of the WLF equation and the polynomial of second degree. The constitutive equations were developed based on the applied boundary conditions and the epoxy compound's mechanical behavior in the respective stage. A two dimensional numerical model was constructed using a commercially available finite element software package. For the experimental verification of the numerically obtained residual stresses a flexible board with the stress measuring chip was encapsulated. The real-time stress data were measured during the encapsulation. Using this technique, the in-plane stresses and the temperature changes during the die encapsulation were measured successfully. Furthermore, the measured stress data was compared with the predicted numerical results of the cure and the thermal stages, independently.