基于FPGA的超声波信号处理设计与实现

为了满足超声波探伤检测的实时性需求,通过研究超声波探伤的工作原理,提出了基于FPGA芯片的实时信号处理系统实现方案及硬件结构设计,并根据FPGA逻辑结构模型实现了软件系统的模块化设计。根据实验测试及统计数据得出,基于FPGA芯片的信号处理系统提高了探伤检测的准确性与稳定性,满足了探伤过程中B超显示的实时性要求。     

基于SOC架构的智能图像处理和外设控制系统设计

针对当前采用的DSP+FPGA实时图像处理和控制系统的不足,提出了一种基于SOC架构的智能图像处理和控制系统,该系统硬件上使用SOC架构进行算法电路实现和外设控制,能够对所获取的图像进行跟踪、识别和匹配等图像处理,同时根据软件配置对外部器件进行控制和交互;通过对大尺寸卷积运算的验证试验,结果表明所设计的SOC架构具有通用性好、可靠性高、处理速度快和控制精准的特点,能够完全适应高复杂的卷积运算。     

FPGA/DSP-based implementation of a high-performance multi-channel counter

A high-performance configurable multi-channel counter is presented. The system has been implemented on a small-size and low-cost Commercial-Off-The-Shelf (COTS) FPGA/DSP-based board, and features 64 input channels, a maximum counting rate of 45 MHz, and a minimum integration window (time resolution) of 24 μs with a 23 b counting depth. In particular, the time resolution depends on both the selected counting bit-depth and the number of acquisition channels: indeed, with a 8 b counting depth, the time resolution reaches the value of 8 μs if all the 64 input channels are enabled, whereas it lowers to 378 ns if only 2 channels are used. Thanks to its flexible architecture and performance, the system is suitable in highly demanding photon counting applications based on SPAD arrays, as well as in many other scientific experiments. Moreover, the collected counting results are both real-time processed and transmitted over a high-speed IEEE 1394 serial link. The same link is used to remotely set up and control the entire acquisition process, thus giving the system a even higher degree of flexibility. Finally, a theoretical model of general use which immediately provides the overall system performance is described. The model is then validated by the reported experimental results.     

An FPGA stereo matching unit based on fuzzy logic

Stereo matching is one of the most used algorithms in real-time image processing applications such as positioning systems for mobile robots, three-dimensional building mapping and recognition, detection and three-dimensional reconstruction of objects. In order to improve the performance, stereo matching algorithms often have been implemented in dedicated hardware such as FPGA or GPU devices. In this paper an FPGA stereo matching unit based on fuzzy logic is described. The proposed algorithm consists of three stages. First, three similarity parameters inherent to each pixel contained in the input stereo pair are computed. Then, the similarity parameters are sent to a fuzzy inference system which determines a fuzzy-similarity value. Finally, the disparity value is defined as the index which maximizes the fuzzy-similarity values (zero up to d_max). Dense disparity maps are computed at a rate of 76 frames per second for input stereo pairs of 1280 × 1024 pixel resolution and a maximum expected disparity equal to 15. The developed FPGA architecture provides reduction of the hardware resource demand compared to other FPGA-based stereo matching algorithms: near to 72.35% for logic units and near to 32.24% for bits of memory. In addition, the developed FPGA architecture increases the processing speed: near to 34.90% pixels per second and outperforms the accuracy of most of real-time stereo matching algorithms in the state of the art.     

A novel hardware plane fitting implementation and applications for bionic vision

This paper presents a high-speed real-time plane fitting implementation on a field-programmable gate array (FPGA) platform. A novel hardware-based least squares algorithm fits planes to patches of points within a depth image captured using a Microsoft Kinect v2 sensor. The validity of a plane fit and the plane parameters are reported for each patch of 11 by 11 depth pixels. The high level of parallelism of operations in the algorithm has allowed for a fast, low-latency hardware implementation on an FPGA that is capable of processing depth data at a rate of 480 frames per second. A hybrid hardware–software end-to-end system integrates the hardware solution with the Kinect v2 sensor via a computer and PCI express communication link to a Terasic TR4 FPGA development board. We have also implemented two proof-of-concept object detection applications as future candidates for bionic vision systems. We show that our complete end-to-end system is capable of running at 60 frames per second. An analysis and characterisation of the Kinect v2 sensor errors has been performed in order to specify logic precision requirements, statistical testing of the validity of a plane fit, and achievable plane fitting angle resolution.     

An FPGA multiprocessor architecture for Bayesian online change point detection using stochastic computation

In this paper we report on an event-based stochastic architecture for the Adams/McKay Bayesian Online Change Point Detection algorithm (BOCPD) [1]. In the stochastic computational structures, probabilities are represented natively as stochastic events and computation is carried out directly with these probabilities and not probability density functions. A fully programmable BOCPD processor is synthesized in VHDL. The BOCPD algorithm with on-line learning, to perform foreground/background image segmentation with online learning. Running on a single Kintex 7 FPGA (Opal Kelly XEM7350-K410T) the architecture is capable of real-time processing a 160 × 120 pixels image, at 10 frames per second.     

三维扫描仪中人头轮廓线提取方法及实现

为解决三维扫描仪的实时性,文章提出了以FPGA处理器与PC主机交互式共同完成提取轮廓线的快速算法。该算法由两个阶段组成:第一阶段由主机计算背景与目标的分割阈值。第二阶段由FPGA处理器实时检测轮廓线位置信息。该快速算法具有计算简单、实现速度快等优点,并且减少了传输与存储的数据量,减轻了后面主机计算工作量。同时,省掉了昂贵的图像采集压缩卡与高速硬盘,降低了成本。可重构FPGA处理器设计成流水线结构,对每个像素的平均处理时间控制在70ns以内。仿真与综合结果表明:从一帧720576标准PAL制视频图像中提取轮廓线信息可在40ms内实时完成。     

An FPGA-based RGBD imager

This paper describes a trinocular stereo vision system using a single chip of FPGA to generate the composite color (RGB) and disparity data stream at video rate, called the RGBD imager. The system uses the triangular configuration of three cameras for synchronous image capture and the trinocular adaptive cooperative algorithm based on local aggregation for smooth and accurate dense disparity mapping. We design a fine-grain parallel and pipelining architecture in FPGA for implementation to achieve a high computational and real-time throughput. A binary floating-point format is customized for data representation to satisfy the wide data range and high computation precision demands in the disparity calculation. Memory management and data bit-width control are applied in the system to reduce the hardware resource consumption and accelerate the processing speed. The system is able to produce dense disparity maps with 320 × 240 pixels in a disparity search range of 64 pixels at the rate of 30 frames per second.     

Evaluation of stereo correspondence algorithms and their implementation on FPGA

The accuracy of stereo vision has been considerably improved in the last decade, but real-time stereo matching is still a challenge for embedded systems where the limited resources do not permit fast operation of sophisticated approaches. This work presents an evaluation of area-based algorithms used for calculating distance in stereoscopic vision systems, their hardware architectures for implementation on FPGA and the cost of their accuracies in terms of FPGA hardware resources. The results show the trade-off between the quality of such maps and the hardware resources which each solution demands, so they serve as a guide for implementing stereo correspondence algorithms in real-time processing systems.     

Harris角点检测的FPGA快速实现方法

针对Harris角点检测算法计算量大导致实时性差的难题,提出了一种基于FPGA的快速Harris角点检测技术。利用FPGA并行处理的特点,将整幅图像分为两块后并行处理,对其中分解得到的每一块图像采用流水线处理,并将流水线结构分为导数生成器、高斯滤波、角点响应R值计算、非极大值抑制四级,且对流水线每一级中涉及到的复杂乘法运算转换为精简的移位及加法或减法运算,最终实现对目标的实时角点检测。实验结果表明,对于分辨率为1024x1024的图像,达到了每帧6.809ms的角点提取速度,与基于FPGA传统结构的Harris角点检测算法相比,速度提高了近一倍,极大提升了算法的实时性,具有较强的工程实用价值。     

Real-time human action recognition on an embedded, reconfigurable video processing architecture

In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. Here we propose a real-time, embedded vision solution for human action recognition, implemented on an FPGA-based ubiquitous device. There are three main contributions in this paper. Firstly, we have developed a fast human action recognition system with simple motion features and a linear support vector machine classifier. The method has been tested on a large, public human action dataset and achieved competitive performance for the temporal template class of approaches, which include “Motion History Image” based techniques. Secondly, we have developed a reconfigurable, FPGA based video processing architecture. One advantage of this architecture is that the system processing performance can be reconfigured for a particular application, with the addition of new or replicated processing cores. Finally, we have successfully implemented a human action recognition system on this reconfigurable architecture. With a small number of human actions (hand gestures), this stand-alone system is operating reliably at 12 frames/s, with an 80% average recognition rate using limited training data. This type of system has applications in security systems, man–machine communications and intelligent environments.

A real-time versatile roadway path extraction and tracking on an FPGA platform

This paper presents an algorithm for roadway path extraction and tracking and its implementation in a Field Programmable Gate Array (FPGA) device. The implementation is particularly suitable for use as a core component of a Lane Departure Warning (LDW) system, which requires high-performance digital image processing as well as low-cost semiconductor devices, appropriate for the high volume production of the automotive market. The FPGA technology proved to be a proper platform to meet these two contrasting requirements. The proposed algorithm is specifically designed to be completely embedded in FPGA hardware to process wide VGA resolution video sequences at 30 frames per second. The main contributions of this work lie in (i) the proper selection, customization and integration of the main functions for road extraction and tracking to cope with the addressed application, and (ii) the subsequent FPGA hardware implementation as a modular architecture of specialized blocks. Experiments on real road scenario video sequences running on the FPGA device illustrate the good performance of the proposed system prototype and its ability to adapt to varying common roadway conditions, without the need for a per-installation calibration procedure.     

基于逆透视变换的车辆排队长度检测方法

交通路口的车辆排队长度检测是智能交通系统的重要组成部分,传统的检测方法易受背景噪声、摄像机透视效果等因素的干扰造成检测失败,而且其实现都是基于串行结构的处理器,不能用于实时处理的场合。本文设计了一种充分利用平直道路几何特征并适合FPGA实现的排队长度自动检测算法,该算法利用逆透视变换消除图像几何失真,引入公路的结构性约束有效检测了车道线;接着采用Sobel边缘算子检测出各车道的车辆轮廓,通过一种基于信息量的度量方法提取排队的队尾,从而确定了车辆排队长度,并且通过硬件化设计使得整个检测过程达到实时的处理速度。     

基于FPGA+GPU的图像采集处理系统设计

随着嵌入式图像处理系统的快速发展,对于前端图像采集模块的需求越来越高。图像采集的速度、分辨率、可靠性以及集成度对后续设计的准确度由极大的影响。通过对数字图像采集系统进行研究,设计出了基于FPGA和GPU架构的图像采集处理系统,重点研究了图像采集处理系统的硬件设计过程和软件设计过程。在基于FPGA+GPU的图像采集处理系统中,让具有强大运算处理能力的GPU专注于数据存储、用户交互以及后续的图像处理。系统中,FPGA则负责图像的采集、外设控制、任务调度。GPU与FPGA之间通过高速PCIE总线进行通信,分别设计编写基于Linux系统的驱动程序和FPGA端PCIE程序。实验结果表明,所设计基于FPGA+GPU的图像采集处理系统可实现437.5Mbps的实时图像采集存储速度,传输过程实时稳定,数据传输完整。     

Scalability and Parallel Execution of Warp Processing: Dynamic Hardware/Software Partitioning

Warp processors are a novel architecture capable of autonomously optimizing an executing application by dynamically re-implementing critical kernels within the software as custom hardware circuits in an on-chip FPGA. Previous research on warp processing focused on low-power embedded systems, incorporating a low-end ARM processor as the main software execution resource. We provide a thorough analysis of the scalability of warp processing by evaluating several possible warp processor implementations, from low-power to high-performance, and by evaluating the potential for parallel execution of the partitioned software and hardware. We further demonstrate that even considering a high-performance 1 GHz embedded processor, warp processing provides the equivalent performance of a 2.4 GHz processor. By further enabling parallel execution between the processes and FPGA, the parallel warp processor execution provides the equivalent performance of a 3.2 GHz processor.     

A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA

Evolvable hardware is a system that modifies its architecture and behavior to adapt with changes of the environment. It is formed by reconfigurable processing elements driven by an evolutionary algorithm. In this paper, we study a reconfigurable HexCell-based systolic array architecture for evolvable systems on FPGA. HexCell is a processing element with a tile-able hexagonal-shaped cell for reconfigurable systolic arrays on FPGAs. The cell has three input ports feed into an internal functional-unit connected to three output ports. The functional-unit is configured using dynamic partial reconfiguration (DPR), and the output ports, in contrast, are configured using virtual reconfiguration circuit (VRC). Our proposed architecture combines the merits of both DPR and VRC to achieve fast reconfiguration and accelerated evolution. A HexCell-based 4 × 4 array was implemented on FPGA and utilized 32.5% look-up tables, 31.3% registers, and 1.4% block RAMs of Artix-7 (XC7Z020) while same-size conventional array consumed 8.7%, 5.1%, and 20.7% of the same FPGA, respectively. As a case study, we used an adaptive image filter as a test application. Results showed that the fitness of the best filters generated by our proposed architecture were generally fitter than those generated by the conventional state-of-the-art systolic array on the selected application. Also, performing 900,000 evaluations on HexCell array was 2.6 × faster than the conventional one.     

Design and VLSI implementation of a high-performance face detection engine

This paper proposes a novel hardware structure and field-programmable gate array (FPGA) implementation method for real-time detection of multiple human faces with robustness against illumination variations. These are designed to greatly improve face detection in various environments with using MCT techniques and the AdaBoost learning algorithm which is robust against variable illumination. We have designed, implemented, and verified the hardware architecture of the face detection engine for high-performance face detection and real-time processing. The face detection chip is developed by verifying and implementing it using a FPGA and an application-specific integrated circuit (ASIC). To verify and implement the chip, we used a Virtex5 LX330 FPGA board and a 0.18 μm 1-poly and 6-metal CMOS logic process. Performance results of the implementation and verification showed it is possible to detect at least 32 faces of a wide variety of sizes at a maximum speed of 147 frames per second.     

Flexible VLIW processor based on FPGA for efficient embedded real-time image processing

Modern field programmable gate array (FPGA) chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance VLIW (very long instruction word) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient ILP (instruction-level parallelism) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors to shorten the development cycle, and to use the powerful FPGA resources to increase real-time performance. We present a flexible VLIW VHDL processor model with a variable instruction set and a customizable architecture which allows exploiting intrinsic parallelism of a target application using advanced compiler technology and implementing it in an optimal manner on FPGA. Some common algorithms of image processing were tested and validated using the proposed development cycle. We also realized the rapid prototyping of embedded contactless palmprint extraction on an FPGA Virtex-6 based board for a biometric application and obtained a processing time of 145.6 ms per image. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability.     

基于ZYNQ的高清图像显示及检测系统设计

针对当前基于ARM和DSP的嵌入式图像处理系统前端采集速度慢和图像处理算法不易加速的缺点,设计了一种基于HDMI接口的全高清(分辨率1920×1080)实时视频采集与图像处理系统;采用500万像素级别CMOS摄像头作为前端数据源,主芯片内部采用ARM+FPGA的异构架构,兼备FPGA的并行处理能力与ARM处理器任务调度功能;基于AXI协议设计了自定义数据存储传输的IP核,实现了处理速度与带宽最大化;利用HLS工具将图像预处理算法快速打包生成IP核,在FPGA中实现图像算法的硬件加速,完成图像处理系统平台原型机的设计;与传统的PC机和相机的机器视觉平台相比,该系统运行平均耗时在10 ms以内,实时检测效果令人满意,有效解决了低功耗与高数据带宽和处理速度之间的矛盾,为后端结果分析和边缘加速提供了良好支持。