Placement of scattering bars in binary and attenuated phase shift mask for damascene trench patterning

Scattering bars have been very effective technique to increase the common lithography process window for patterns with design rules 0.18 μm and below. This paper studies the placement of scattering bars in binary and attenuated phase shift mask in damascene trench patterning. Different partial coherence values are used to compare the scattering bar effect in binary and 8% attenuated phase shift mask. At low partial coherence (σ) the trench size has been found more sensitive to scattering bar parameters than at high σ. Scattering bar separation is found more effective than size to affect the trench critical dimension (CD). At low partial coherence a deep valley or ‘V’ shaped CD trend is found in scattering bar separation versus CD curve. CD dip is more using APSM as compared to binary mask. The process latitude is poor at valley as compared to top. Also, 3 sigma CD variation and range is higher at valley as compared to other separations of the scattering bars.     

Potential applications of negative tone development in advanced lithography

Advanced lithography requires resolution enhancement techniques (customized illumination mode, litho friendly design), and alternative process flow schemes (double exposure, double patterning) in order to meet the requirements of the ITRS technology roadmap and to extend the applications of a full-field scanner with a 1.35 numerical aperture (NA) that represents the physical limit of water-based immersion ArF lithography.Today, one of the most interesting alternative processes uses the patterning inversion through a negative tone development (NTD) process step. Traditionally, the patterning (contacts or trenches) is done by using a dark field mask in combination with positive tone resist and positive tone development (PTD). By using a solvent-based developer (NTD) and a bright field mask, the same features can be transferred into a positive resist with the benefit of better image contrast and, consequently, better line width roughness (LWR) and resolution.In this work we have explored the potential applications of NTD for trenches and contact holes for the 45 nm technology node requirements and beyond. The NTD process is a promising option considering the impact on process window, LWR, CD uniformity and defectivity. The experimental result of this alternative approach to print critical dark field levels in an advanced lithography boundary has been explored.     

A study of projected optical images for typical IC mask patterns illuminated by partially coherent light

Optical projection printing using partially coherent illumination is simulated for one micrometer and half micrometer objects representative of typical mask patterns such as contact holes, rectangular bars and openings, intersections of perpendicular lines, and adjacent lines of unequal lengths. The image intensity distributions in absorptionless photoresists on nonreflective substrates are plotted as sets of constant intensity contours. For each pattern and illumination, an exposure-defocus (E-D) diagram is generated by evaluating the combined exposure and defocus tolerance yielding linewidths within ±2.5 percent of the mask linewidth. Besides comparing the image and ED margins of different object shapes and sizes, the effects of high versus low degrees of coherence, single versus dual wavelength, as well as long-wavelength high NA versus short-wavelength low NA were studied using the 1-µm rectangular opening.     

Robust defocus blur identification in the context of blind image quality assessment

A defocus blur metric for use in blind image quality assessment is proposed. Blind image deconvolution methods are used to determine the metric. Existing direct deconvolution methods based on the cepstrum, bicepstrum and on a spectral subtraction technique are compared across 210 images. A variation of the spectral subtraction method, based on a power spectrum surface of revolution, is proposed and is found to compare favourably with existing direct deconvolution methods for defocus blur identification. The method is found to be especially useful when distinguishing between in-focus and out-of-focus images.     

Effect of PVP-coated silver nanoparticles using laser direct patterning process by photothermal effect

Laser direct patterning of silver nanoparticles (AgNPs) conductive patterns on a polyimide substrate using photothermal effect of nanoparticles provides various advantages for applications in flexible electronics. Two PVP content AgNPs were used in this research. Since the thin and thick PVP-coated AgNPs have a strong optical absorption at 426 and 405 nm, respectively, a UV laser (405 nm and 60 mW) is used to trigger AgNPs to convert light into heat due to photothermal effect of nanoparticles. After UV laser beam irradiating on the AgNPs thin film, the AgNPs aggregate into larger conducting grains and improve the adhesion between AgNPs and the polyimide substrate at the same time. Then the desired AgNPs conductive lines (line width: 30 μm, line space: 70 μm) are formed after washing the unirradiated AgNPs. By this method, we have demonstrated a 5 μm width AgNPs conductive line. In the mean time, we also found out that the higher PVP content, the laser direct patterning of AgNPs conductive lines would have more straight and smooth boundaries. And the adhesion between the AgNPs conductive patterns and PI substrate would be better while using higher PVP content AgNPs.     

Simulation and verification of void transfer patterning (VTP) technique for nm-scale features

This paper investigates simulation of a patterning technique for defining sub-lithographic features. The technique studied involves intentional creation of voids using a conformal chemical vapor deposition (CVD) followed by controlled etch-back to form nanoscale pores. This method provides features that are independent of lithographically defined parent holes and exhibit lower critical dimension (CD) variations. It offers efficient low thermal budget and backend process compatible integration scheme that requires just one additional mask level. The void diameter obtained in this work is 74 nm i.e. ∼10× reduction from lithographically defined hole of 714 nm using i-line lithography. Critical parameters affecting the void formation and the final pore size have been identified and modeled. Simulation of the void transfer process has been investigated using plasma etch module of ‘Elite’ by Silvaco that employs 2-D Monte Carlo ion transport modeling. The results of this investigation show that the geometrical design parameters can be coupled with the plasma process simulations to develop an efficient module for the void transfer process.     

Spatially variant defocus blur map estimation and deblurring from a single image

In this paper, we propose a single image deblurring algorithm to remove spatially variant defocus blur based on the estimated blur map. Firstly, we estimate the blur map from a single image by utilizing the edge information and K nearest neighbors (KNN) matting interpolation. Secondly, the local kernels are derived by segmenting the blur map according to the blur amount of local regions and image contours. Thirdly, we adopt a BM3D-based non-blind deconvolution algorithm to restore the latent image. Finally, ringing artifacts and noise are detected and removed, to obtain a high quality in-focus image. Experimental results on real defocus blurred images demonstrate that our proposed algorithm outperforms some state-of-the-art approaches.     

TiNx as a new embedded material for attenuated phase shift mask

In this paper TiNx (x > 1.3) as a new material suitable for using as an embedded layer for an attenuated phase shift mask (APSM) is presented. TiNx thin film was formed by plasma sputtering under a gas mixture of Ar and N₂ (40:2 sccm). The related characteristics of TiNx at 365 nm (i-line) wavelength are as follows: n (refractive index) 3.07; k (absorbance coefficient) 0.531; R (reflectivity) 2730%; (resistivity) 52 μΩ-cm (132 nm on quartz). For required phase shift degree θ = 180°, calculated thickness d of TiNx film is 88.2 nm, and transmittance T under 365 nm wavelength at this thickness is 14.5 % which is within the useful range for APSM. TiNx film also has good electrical conductivity, suitable for e-beam direct-write in patterning mask.     

Subtractive contact-patterning of molecular organic films

An array of optoelectronic applications requires micro- and nanoscale patterning of molecular organic films. A subtractive patterning technique is developed to define micron-sized features of nanometer range thickness on a variety of hole transporting and hole blocking materials. Lateral resolution of patterned features is controlled by micron-scale stamp shapes, while the removal of the patterned nanoscale film thicknesses (sub-10 nm to over 40 nm) is correlated to strength of interfacial and intermolecular forces. Using this process, a multi-color organic light-emitting device is fabricated, demonstrating the ability of contact patterning to manipulate organic molecular films on the micro- and nanoscales.     

Low voltage CCD image sensor with optimized reset operation

A charge coupled device (CCD) image sensor operating with 3.0 V-reset has been developed using a charge injection to the gate dielectrics of a MOS structure. A DC bias generating circuit was added to the reset structure, which sets reference voltage and holds the signal charge to be detected. The generated Dc bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2 to 5.5 V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with 492(H)×510(V) pixels adopting this structure showed complete reset operation with the driving voltage of 3.0 V. The image taken with the image sensor utilizing this structure was not saturated to the illumination of 30 lux, that is, showed no image distortion.     

Capacitance-voltage analysis of InAs quantum dots grown on InAlAs/InP(0 0 1)

The electronic properties of InAs quantum dots (QDs) grown on InAlAs/InP(0 0 1) were studied by using capacitance-voltage (C-V) analysis and photoluminescence (PL) measurements. The level positions of electrons and holes could be studied separately by using n- and p-type InAlAs matrices, respectively. The holes are found to be more confined than electrons in these kinds of dots.     

Temperature behavior and modeling of ohmic contacts to Si implanted n-type GaN

The behavior of an ohmic contact to an implanted Si GaN n-well in the temperature range of 25-300 °C has been investigated. This is the sort of contact one would expect in many GaN based devices such as (source/drain) in a metal-oxide-semiconductor transistor. A low resistivity ohmic contact was achieved using the metal combination of Ti (350 Å)/Al (1150 Å) on a protected (SiO₂ cap) and unprotected samples during the post implantation annealing. Sheet resistance of the implanted layer and metal-semiconductor contact resistance to N⁺ GaN have been extracted at different temperatures. Both, the experimental sheet resistance and the contact resistance decrease with the temperature and their characteristics are fitted by means of physical based models.     

Al contacts to nanoroughened p-GaN

Nanoroughening of a p-GaN surface using nanoscale Ni islands as an etch mask was utilized to investigate the feasibility for the flip-chip configuration light-emitting diodes (LEDs) using an Al-based reflector. Improved ohmic characteristics were found for the nanoroughened sample. A specific contact resistivity of 8.9×10⁻² Ω cm² and a reflectance of 82% at 460 nm were measured for the nanoroughened Al contact. The Schottky barrier heights were decreased from 0.81 eV (I-V) and 0.84 eV (Norde) for the Al contact to 0.70 eV (I-V) and 0.69 eV (Norde) for the nanoroughened Al contact. The barrier height reduction may be attributed to enhanced tunneling and the increased contact area due to the nanoroughening. This work suggests that the ohmic contact characteristics and the light extraction efficiency may be improved further with a well-defined nanopatterned p-GaN layer.     

Study of deep level defect behavior in undoped n-InP (1 0 0) after rapid thermal annealing

The effects of rapid thermal annealing on deep level defects in the undoped n-type InP with Ru as Schottky contact metal have been characterized using deep level transient spectroscopy (DLTS). It is observed that the as-deposited sample exhibit two deep levels with activation energies of 0.66 and 0.89 eV. For the samples annealed at 300 °C and 400 °C, a deep level is identified with activation energies 0.89 and 0.70 eV, respectively below the conduction band. When the sample is annealed at 500 °C, three deep levels are observed with activation energies 0.25, 0.32 and 0.66 eV. Annealing of the sample at 300 °C, orders the lattice of as-grown material by suppressing the defect 0.66 eV (A1) which is found in the as-deposited sample. The trap concentration of the 0.89 eV deep levels is found to be increased with annealing temperature. The deep level 0.32 eV may be due to the lattice defect by thermal damage during rapid thermal annealing process such as vacancies, interstitials and its complexes, indicating the damage of the sample after annealing at 500 °C. The defects observed in all the samples are possibly due to the creation of phosphorous vacancy or phosphorous antisite.     

Stencil-assisted reactive ion etching for micro and nano patterning

Stencil-assisted oxygen reactive ion etching is a low-cost and parallel process for the replication of micrometric and nanometric patterns in any organic material. This lithography process allows the patterning of organic material non sensitive to electronic or optical radiations, sensitive to solvents, or already patterned which cannot be patterned by conventional lithography methods. We demonstrate the versatility of stencil-assisted reactive ion etching though 3 examples. First to define 500 nm holes in PMMA. Secondly, the fabrication step has been integrated in a lift-off process of metal or molecular self-assembled monolayers. We finally apply stencil-assisted reactive ion etching to pattern an assembly of 100 nm latex nanoparticles.     

Dry etching fin process for SOI finFET manufacturing: Transition from 32 to 22 nm node on a 6T-SRAM cell

This work describes the main challenges encountered for patterning crystalline silicon (c-Si) fins when we scaled down the fin pitch from 124 to 90 nm on a 6T-SRAM cell. The target fins consist of straight structures (40 nm height and 17 nm of critical dimension) patterned on a 22 nm node with 90 nm fin pitch. The patterning stack consists of 70 nm of amorphous carbon as a hard mask with 25 nm of antireflective coating. Scaling down the fin pitch had a direct influence on the fin critical dimension, profile and sidewall roughness. We found out that the fin etching process developed for a 32 nm node with 124 nm fin pitch was no longer functional for patterning fins on a 22 nm node with 90 nm fin pitch, i.e., the critical dimension was wider than the target, the fins sidewalls were isotropically attacked and the profile was sloped. In order to reach 17 nm of critical dimension on 90 nm pitch we had to implement a new hard mask opening step. The c-Si fin sidewall roughness and fin profile were tuned by improving the uniformity across the wafers, optimizing the softlanding etch time and introducing a new overetch step with notch capability.     

Investigation on the effect of annealing process parameters on AuGeNi ohmic contact to n-GaAs using microstructural characteristics

The electrical and structural properties of AuGeNi ohmic contact to n-GaAs have been studied. A combination of EDX and X-ray diffraction analysis was used to examine the reactions between AuGeNi-based metallization and GaAs. Scanning Tunneling Microscope (STM) was used to study surface morphology and surface roughness. By the use of Rapid Thermal Annealing (RTA), contact resistivity as low as 5.5 × 10⁻⁸ Ω cm² have been obtained. The minimum in the contact resistivity coincides with the formation of AuGa and NiAs phases. On the other hand, poor thermal stability after contact formation was concluded to be due to the formation of low melting point AuGa phases. Formation of dark particles, recognized as GeNi particles, in different distributions and shapes after annealing, was found to be essential for low contact resistivity. Correlation between GeNi particles distribution and contact resistivity was found and introduced as d/λ parameter. It was found that the lower the size of these particles (d) as well as the larger the contact area over which they are distributed (λ) leading to the better contact resistivity.     

Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density

We present a method to obtain Si-fins with a critical dimension (CD) below 20 nm, separated by a minimum distance of 25 nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350 nm pitch resist pattern defined by 193 nm lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200 mm wafer. The average CD is 17 nm in the center of the wafer and 18 nm at the edge. The LWR is 3 nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H₂ anneal) further reduce the CD to 13 nm.     

The etchback approach: Enlarged process window for MuGFET gate etching

We present a new method to enlarge the process window for gate patterning on a surface with high topography. We have compared two approaches for the patterning of a poly-Si gate with oxide hard mask (HM) as used in multi-gate field effect transistors. In the first approach, referred to as ‘direct deposition’, a poly-Si layer of 60 nm is deposited on the substrate, whereas in the second, and new approach 200 nm poly-Si is deposited and anisotropically etched back to 60 nm. All subsequent process steps (i.e. HM deposition, lithography and gate etch) are identical. From ellipsometric thickness measurements, we conclude that for the etchback case the poly-Si film has a larger within-wafer-non-uniformity due to the deposition of a thicker film. On the other hand, top down and cross-section SEM after gate etch show that for the etchback approach there is a larger process window with respect to avoiding micro-masking by the oxide HM at topography steps. We demonstrate that less over-etch is needed during the HM opening step to achieve residue free patterning of the poly-Si film. For a poly-Si thickness of 100 nm, we were able to obtain a residue free gate etch process for both the direct deposition and the etchback approach. Electrical evaluation shows that device performance is not compromised when using the etchback approach.     

Flexible thin-film transistors using multistep UV nanoimprint lithography

A multistep imprinting process is presented for the fabrication of a bottom-contact, bottom-gate thin-film transistor (TFT) on poly(ethylene naphthalate) (PEN) foil by patterning all layers of the metal–insulator–metal stack by UV nanoimprint lithography (UV NIL). The flexible TFTs were fabricated on a planarization layer, patterned in a novel way by UV NIL, on a foil reversibly glued to a Si carrier. This planarization step enhances the dimensional stability and flatness of the foil and thus results in a thinner and more homogeneous residual layer. The fabricated TFTs have been electrically characterized as demonstrators of the here developed fully UV NIL-based patterning process on PEN foil, and compared to TFTs made on Si with the same process. TFTs with channel lengths from 5 μm down to 250 nm have been fabricated on Si and PEN foil, showing channel length-dependent charge carrier mobilities, μ, in the range of 0.06–0.92 cm² V⁻¹ s⁻¹ on Si and of 0.16–0.56 cm² V⁻¹ s⁻¹ on PEN foil.