模糊联想记忆网络的增强学习算法

针对 Kosko提出的最大最小模糊联想记忆网络存在的问题 ,通过对这种网络连接权学习规则的改进 ,给出了另一种权重学习规则 ,即把 Kosko的前馈模糊联想记忆模型发展成为模糊双向联想记忆模型 ,并由此给出了模糊快速增强学习算法 ,该算法能存储任意给定的多值训练模式对集 .其中对于存储二值模式对集 ,由于其连接权值取值 0或 1,因而该算法易于硬件电路和光学实现 .实验结果表明 ,模糊快速增强学习算法是行之有效的 .     

具有抗随机噪声能力的联想记忆网络

形态联想记忆网络具有良好的联想记忆功能和较强的抗膨胀或腐蚀噪声能力,但抗混合噪声的能力很弱.而在实际中,随机噪声往往是混合型的,既有膨胀又有腐蚀噪声,将尺度空间和形态联想记忆网络相结合,得到了一种新的联想记忆网络,它提高了形态自联想记忆网络的抗随机噪声能力.通过仿真实验验证了该方法具有良好的性能.     

复形态双向联想记忆网络及其性能分析

基于复数环(C,∨,∧,+)提出了复形态双向联想记忆网络模型,给出了神经网络实现双向完全联想记忆的条件,并分析了自联想的存储能力、稳定性和收敛性及神经网络的抗噪声能力.当复数虚部取零时即为实数,实数域形态双向联想记忆网络就是复数域形态双向联想记忆网络的特例.最后通过仿真实验验证复形态双向联想记忆网络的有效性.     

基于小世界体系的核自联想记忆模型

1引言 联想记忆神经网络是体现网络优势、具有广泛应用前景的一类网络模型.本文借鉴近年来机器学习领域中颇具影响力的核方法[1]和社会网络中广泛存在的小世界体系[2],通过改进Hopfield联想记忆模型的回忆规则[3],构建了一类基于小世界体系的核自联想记忆模型(small world architecture basedkernel auto-associative memory model,SWAKAM).在FERET人脸数据库上的测试表明,它获得了比标准的特征脸算法(PCA)[4]以及最近提出的E(PC)2A[5]算法更高的识别率.SWA-KAM模型所具有的最大特点是,它以较小的代价获得了较高的性能,较大地简化了全互连KAM模型的结构,使传统AM模型的VLSI实现更加容易.     

一个新的高阶双向联想记忆模型及其性能估计

提出了一个新的高阶双向联想记忆模型.它推广了由Tai及Jeng所提出的高阶双向联想记忆模型HOBAM(higher-order bidirectional associative memory)及修正的具有内连接的双向联想记忆模型MIBAM(modified intraconnected bidirectional associative memory),通过定义能量函数,证明了新模型在同步与异步更新方式下的稳定性,从而能够保证所有被训练模式对成为该模型的渐近稳定点.借助统计分析原理,估计了所提模型的存储容量.计算机模拟证实此模型不仅具有较高的存储容量,而且还具有较好的纠错能力.     

具有期望容错域的前向掩蔽联想记忆模型的设计方法

联想记忆的综合问题是目前没有很好解决的难题.文中用作者提出的通用前馈网络和排序学习算法,提出了一种设计具有期望容错域的前向掩蔽联想记忆模型的方法.该方法一般性地解决了信息空间上联想记忆的综合难题,使设计出的联想记忆模型具有任意期望的记忆样本容错域.     

小世界神经网络中的联想记忆研究

本文研究了基于小世界结构的神经网络中的联想记忆模型.网络恢复存储模式的行为其实是无序参数为一有限值时的相位变化.越是规则的网络越是难以恢复记忆模式,且容易变成混合状态.另外,在无序参数的值适中时,对于一定数量的存储模式,最终得到恢复的效果可以达到最大.     

基于混沌神经网络的电机故障诊断

采用全局耦合混沌神经网络模型，每个神经元的动力学行为由反对称立方映像表示。采用Hebb算法设计网络的连接权值矩阵．将记忆模式的回忆过程转化为耦合系统中参数演变的过程，从而实现了混沌神经网络的联想记忆。根据提出的能量击穿规则，扩大了样表的吸引域。在此基础上，应用该混沌神经网络对异步电机转子断条故障进行诊断。结果表明，该种方法有助于故障模式的记忆和重现。     

讲座：人工神经网络：第四讲 反馈网络与联想记忆（续）

4基本学习规则Hopfield网络的学习，采用的是无导师学习。学习的过程相应于形成网络的连接权矩阵W。讨论的中心问题在于，如何使网络对于给定的问题进行学习，建立连接权矩阵，并使网络具有较强的联想记忆能力。假设需要存贮的记忆样本有P个X1，X2，…，XPXi∈{－1， 1}n（1）Hebb学习规则a．对一个模式的学习为了分析简便，首先考虑网络对一个模式的学习。这时需要存贮的记忆样本只有1个（设为X1），它将成为网络的稳定状态，并具有最大的吸引域，或者说具有最大的“纠错能力”。将记忆样本X1输入到网络，并作为网络的初始状态，经过…     

复形态联想记忆及其性能分析

在Ritter的实域形态联想记忆(real morphological associative memory,简称RMAM)模型的基础上,通过在复数域中序关系的引入构成复数格和环,导出了在复数域上与RMAM相一致的联想规则,构建了一类复域MAM(complex MAM,简称CMAM),从而将RMAM从实域推广至复域,使其可直接处理复信号(如经FFT(fast Fourier Transformation)变换所得数据).证明了该模型的收敛性,分析了其纠错能力和存储能力,并获得了与RMAM相一致的一系列定理和性质.此外,还比较了复形态网络和其他网络(如Hopfield神经网络)的异同.计算机仿真结果表明了CMAM的可行性.     

多核处理器并行计算模型研究

针对并行计算机体系结构中没有通用的计算模型这一问题,分析了一些现有的典型计算模型,在同步性、通信方式、参数方面进行比较,以LogGP模型为基础提出一种改进的mzLogGP模型。利用MPI并行算法对满足节点计算资源非独占、网络存在拥塞条件下的并行程序进行分析与测试,通过增加memory层次化层数和网络拥塞指数这两个参数,计算其计算开销和通信开销,将实测时间与预测时间进行比较,可知随节点数的增加系统误差不断减小,说明该新模型能改善并行应用在多核处理器集群平台上运行的性能,具有较好的可扩展性。     

Direct distributed memory access for CMPs

On-chip distributed memory has emerged as a promising memory organization for future many-core systems, since it efficiently exploits memory level parallelism and can lighten off the load on each memory module by providing a comparable number of memory interfaces with on-chip cores. The packet-based memory access model (PDMA) has provided a scalable and flexible solution for distributed memory management, but suffers from complicated and costly on-chip network protocol translation and massive interferences among packets, which leads to unpredictable performance. In this paper we propose a direct distributed memory access (DDMA) model, in which remote memory can be directly accessed by local cores via remote-to-local virtualization, without network protocol translation. From the perspective of local cores, remote memory controllers (MC) can be directly manipulated through accessing the local agent MC, which is responsible for accessing remote memory through high-performance inter-tile communication. We further discuss some detailed architecture supports for the DDMA model, including the memory interface design, work flow and the protocols involved. Simulation results of executing PARSEC benchmarks show that our DDMA architecture outperforms PDMA in terms of both average memory access latency and IPC by 17.8% and 16.6% respectively on average. Besides, DDMA can better manage congested memory traffic, since a reduction of bandwidth in running memory-intensive SPEC2006 workloads only incurs 18.9% performance penalty, compared with 38.3% for PDMA.     

A context switching streaming memory architecture to accelerate a neocortex model

A novel architecture to accelerate a neocortex inspired cognitive model is presented. The architecture utilizes a collection of context switchable processing elements (PEs). This enables time multiplexing of nodes in the model onto available PEs. A streaming memory system is designed to enable high-throughput computation and efficient use of memory resources. Several scheduling algorithms were examined to efficiently assign network nodes to the PEs. Multiple parallel FPGA-accelerated implementations were evaluated on a Cray XD1. Networks of varying complexity were tested and indicate that hardware acceleration can provide an average throughput gain of 184 times over equivalent parallel software implementations.     

内存数据库技术在电网实时监测中的应用研究

对现有的内存数据库体系结构进行了改进,引进了数据失步缓冲机制和自适应文件缓冲机制,并将改进后的内存数据库技术整合到企业电网实时监测系统的整体架构中,提出了一套完整的基于内存数据库技术的企业电网实时监测系统的架构模型,该模型在保证数据实时性的同时可提高监测系统的并行处理能力和稳定性.与内存数据库相关的数据接口访问、数据同步等关键技术也进行了详细的分析,最后给出了系统的实际应用案例.     

A scalable high-performance computing solution for networks onchips

The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs     

Memory and Network Architecture Interaction in an Optically Interconnected Distributed Shared Memory System

This paper develops a performance model of an optically interconnected parallel computer system operating in a distributed shared memory environment. The performance model is developed to reflect the impact of low level optical media access protocol and optical device switching latency on high level system performance. This enables the model to predict the performance impact of supporting distributed shared memory with different address allocation schemes and media access protocols. The passive star-coupled photonic network operates through wavelength division multiple access. Two media access protocols are examined for this WDM network, both are designed to operate in a multiple-channel multiple-access environment and require each node to possess a wavelength tunable transmitter and a fixed (or slow tunable) receiver. A semi-Markov model has been developed to study the interaction of the distributed shared memory architecture and the two access protocols of the photonic network. This analytical model has been validated by extensive simulation. The model is then used to examine the system performance with varying numbers of nodes and wavelength channels and varying, memory and channel access times.     

Memory capacity and information capacity of sparsely encoded associative memory with replacement units

We introduce sparse encoding into the autoassociative memory model with replacement units. Utilizing computer simulation, we search the optimal number of replacement units in two terms: the memory capacity and the information capacity of the network. We show that the optimal number of replacement units to maximize the memory capacity and the information capacity decreases as the firing ratio decreases, and that the difference in the memory capacity between sparse encoding and non-sparse encoding becomes small as the number of replacement units increases.     

高带宽远程内存结构中的预取研究

高速电路和光互联技术的发展极大地提高了网络的速度与带宽。因而,突破高性能计算机CPU与内存紧耦合的传统结构成为可能,CPU与内存的耦合不再受距离的限制,这必将引起体系结构的变革。文[1]提出DSAG结构——CPU与内存在空间上分离,每个CPU节点上仅留少量内存．将海量内存放在远程统一管理作为内存服务器,CPU节点和内存服务器之间通过高速网络互连。这种新的体系结构带来了更好的共享性和可扩展性,但同时也对我们解决CPU和内存之间的不平衡性问题带来了挑战。为了降低DSAG这种远程内存结构增加的访存时延,我们考虑到CPU正常访存没有充分利用网络的高带宽,因此可以利用剩余的网络带宽来进行远程内存数据的预取。本论文在应用程序执行时记录本地（相对于远程内存）不命中的地址信息,以页对齐分析其中存在的页框流（Page Frame Stream）的统计特征,并提出可基于页框流的预取机制可降低访存延迟、提升系统性能的观点。最后我们采用模拟的方法验证了观点的可行性与正确性,进一步提出了三种预取策略,比较并分析影响预取效果的因素。     

A parallel logic system on a multicomputer architecture

This paper describes the implementation of a logic programming language on a massively parallel architecture. This implementation is based on the AND/OR Process Model which allows the exploitation of both AND and OR parallelism in logic programs. A distributed memory model is used, and a decentralized control mechanism has been designed. The multicomputer, which the system has been implemented on, consists of a network of Inmos Transputers. The AND/OR processes are implemented as Occam processes mapped onto the Transputer nodes. After the presentation of the system architecture and a deep discussion of the distributed memory management, some preliminary performance results are discussed.     

基于MPMF算法的高速网络内容审计系统架构

介绍了高速网络内容审计系统的主要组成部分，提出了将内容审计系统的过程模型分为流水线模型和分段模型。提出了一种针对流水线模型的MPMF反馈算法，该算法利用系统各个部分的内存使用情况，对负载均衡器做出不同优先级的反馈，有效地利用了系统资源，并给出了一种满负荷情况下“半截会话”问题的解决方案。