一种基于电压控制电流源的单片LDO稳压器的设计与实现

提出了一种单片集成的高电源抑制比LDO稳压器,主要应用于PLL中VCO和电荷泵的电源供给。该稳压器采用电压控制电流源（VCCS）补偿方案,与其他补偿方法相比,VCCS补偿仅需要一个0.18 pF的电容。误差放大器采用折叠共源共栅结构,可以提供高的电源抑制比,并且使得设计的LDO为两级放大器结构,有利于简化补偿网络。文中设计的LDO在低频时电源抑制比（PSR）为-58.7 dB,在1MHz处的电源抑制比为-20 dB。采用0.35 µm CMOS工艺流片,测试结果表明,本文设计的LDO可以为负载提供50 mA的电流。     

LDO线性稳压器中高性能误差放大器的设计

设计了一个共源共栅运算跨导放大器,并成功地将其应用在一款超低功耗LDO线性稳压器芯片中。该设计提高了电源抑制比(PSRR),并具有较高的共模抑制比(CMRR)。电路结构简单,静态电流低。该芯片获得了高达99 dB的电源抑制比。     

一种全负载稳定的高PSRR LDO的设计北大核心CSCD

提出了一种高电源纹波抑制比的低压差线性稳压器.该低压差线性稳压器通过提高带隙基准的电源抑制比以达到提高LDO(低压差线性稳压器)低频电源纹波抑制的能力.在TSMC 0.18μm CMOS工艺下进行了仿真验证,仿真结果表明,该LDO最大负载电流可以达到80mA,当负载电流在0~80mA范围内变化时,开环相位裕度均大于64°,证明了低压差线性稳压器的高稳定性.当负载电流从0mA跳变到80mA时,系统的输出电压过冲仅为15mV,环路响应时间仅为0.5μs.当负载电流为80mA,测得10kHz时的电源纹波抑制比为-60.82dB,100kHz时LDO的电源纹波抑制比为-57.66dB.     

用于植入式医疗设备的高PSRR无片外电容LDO

提出了一种用于植入式医疗设备的高电源抑制比(PSRR)无片外电容的低压差线性稳压器(LDO)。所设计的LDO采用自适应负载电流追踪的前馈纹波消除技术来产生动态的前馈纹波,以改善其在不同负载电流下的PSRR。LDO采用超级源跟随器和密勒补偿电路来保证电路的稳定性,其只需要1.2 pF的片上电容。电路采用TSMC 0.18 μm CMOS工艺设计与仿真。仿真结果表明,当负载电流为1 mA时,该LDO的PSRR在1 MHz处为-56.7 dB,在10 MHz处为-45 dB,比传统LDO分别改善了24 dB和30 dB;当负载电流为10 mA时,该LDO的PSRR在1 MHz处为-55.6 dB,在10 MHz处为-43 dB,比传统LDO分别改善了20 dB和28 dB。     

一种适用于LDO的三级误差放大器的设计

为了促进LDO在低电源电压环境中的应用,提高其稳定性,在此采用SMIC0．35um,N阱CMOS工艺,设计并实现了适用于LDO内部误差放大器的一种单密勒电容频率补偿的三级CMOS运算放大器。仿真结果表明该运算放大器的工作电压范围宽（2．5～6．5V）,静态电流小,开环电压增益为112．16dB,相位裕度为89．03°,增益带宽积为6．04MHz,共模抑制比为89．3dB,电源抑制比为104．8dB。     

用于无源RFID标签的拓展PSRR带宽无片外电容LDO

经过调制的射频信号整流后会为无源射频识别(RFID)标签引入数万到几十万赫兹的电源纹波.为了抑制这种电源纹波,设计了一款1 MHz带宽内高电源电压抑制比(PSRR)、超低功耗、无片外电容低压差线性稳压器(LDO).利用超级源跟随器结构改变传统LDO环路的极点分布,将输出极点作为环路主极点,将低频PSRR带宽有效拓展到1 MHz.利用动态偏置技术和双零点补偿结构保证环路稳定性.该LDO采用TSMC 0.18 μm CMOS工艺实现,芯片面积约0.017 mm2.测试结果表明:LDO在1 MHz频率范围内的PSRR小于-46 dB,轻负载下的PSRR可达-57 dB;电路消耗0.33～3.4 μA的静态电流;在工作电压为1.1～3 V时输入电压调整率为4.6 mV/V;在负载电流为0～25 μA时负载调整率为0.3 mV/μA;该LDO仅采用35 pF片上电容.     

一种用于RF供电的混合结构DC-DC变换器

设计了一种基于0.13 μm CMOS工艺的混合结构DC-DC变换器。该变换器由Buck变换器和LDO串联组成。Buck变换器输出电压可根据LDO负载电流进行调节,能有效减小LDO损耗。在负载电流为20 mA时,可将整个变换器的效率提高10.5%。LDO采用片外电容补偿。高带宽误差放大器使LDO在DC~20 MHz范围内具有较高的电源抑制比。LDO对Buck变换器开关频率处的噪声抑制达-62 dB。整个电源具有较低的输出噪声,适于为RF电路供电。     

应用于红外焦平面读出电路的片上LDO设计

低压差线性稳压器(low-dropout voltage regulator,LDO)由于具有响应速度快、芯片面积小、低输出噪声的优点,很适合作为电源模块集成到红外焦平面读出电路的系统中。设计了一款低噪声、带buffer和密勒补偿的LDO结构的线性电源,芯片采用CSMC 0.6 μm CMOS工艺设计,在Hspice上对电路模块进行了仿真验证。仿真结果表明,该LDO在50 kHz、3.3~5 V的电源电压下,线性调整率最大为10 mV/V,电源抑制比(PSRR)为50 dB,负载电流可达到100 mA。     

高稳定性无片外电容低压差线性稳压器的设计

设计了一款无片外电容低压差线性稳压器(LDO),与传统的LDO相比,此LDO消除了传统结构中所需的片外电容,可更好地应用于全集成低功耗的片上系统(SoC)中。针对无片外电容LDO没有外部等效零点补偿这一特点,采用一种折叠输入推挽输出误差放大器结构,结合密勒补偿以及一阶RC串联零点补偿两种方案,有效地改善了无片外电容LDO的稳定性。电路采用SMIC0.18μm CMOS工艺实现,面积为0.11 mm2,最大负载电容100 pF,输入电压为1.8 V时,输出电压为1.5 V,静态电流31.8μA,压差为160 mV。     

一种高电源抑制比LDO

采用0.18 μm CMOS工艺,设计了一种低压差线性稳压器(LDO)。分析了传统LDO在重载高频下电源抑制比(PSR)的缺陷,提出一种带有多级缓冲PSR提升结构的LDO。采用创新的PSR增强结构,使得PSR增强效果与其负载电流成弱相关,从而保证LDO在宽负载范围内具有优秀的高频PSR增强效果。仿真结果表明,负载电流为300 mA时,低频下LDO的PSR为-68 dB,频率为10 MHz时LDO的PSR可达－50 dB。     

A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

A full on-chip CMOS low-dropout(LDO) voltage regulator with high PSR is presented.Instead of relying on the zero generated by the load capacitor and its equivalent series resistance,the proposed LDO generates a zero by voltage-controlled current sources for stability.The compensating capacitor for the proposed scheme is only 0.18 pF,which is much smaller than the capacitor of the conventional compensation scheme.The full on-chip LDO was fabricated in commercial 0.35μm CMOS technology.The active chip area...     

A fast-transient high-PSR output-capacitor-free low-dropout regulator for low-power embedded systems

A low-power fast-transient output-capacitor-free low-dropout regulator (LDO) with high power-supply rejection (PSR) is presented in this paper. The proposed LDO utilizes a non-symmetrical class-AB amplifier as the input stage to improve the transient performances. Meanwhile, PSR enhancement circuit, which only consumes 0.2-µA quiescent current at light load, is utilized to form a feedforward cancellation path for improving PSR over wide frequency range. The LDO has been designed and simulated in a mixed signal 0.13-µm CMOS process. From the post simulation results, the LDO is capable of delivering 100-mA output current at 0.2-V dropout voltage, with 3.8-µA quiescent current at light load. The undershoot, the overshoot and the 1 % settling time of the proposed LDO with load current switching from 50 µA to 100 mA in 300 ns are about 100 mV, 100 mV and 1 µs, respectively. With the help of proposed PSR enhancement technique, the LDO achieves a PSR of ?69 dB at 100 kHz frequency for a 100-mA load current.     

PSR enhancement techniques for output-capacitor-free LDO regulator design

In this paper, power-supply rejection (PSR) enhancement techniques for a output-capacitor-free low drop-out (LDO) regulator with an NMOS pass transistor are presented. For DC PSR and bandwidth enhancement, DC PSR compensation and capacitor cancelation circuits were developed on the basis of precisely derived PSR models of the conventional LDO regulator. The effectiveness of the PSR enhancement techniques were verified using analytic PSR models, SPICE simulation, and measurements. The fabricated LDO regulator using 0.18 \(\upmu\)m CMOS technology maintains PSR less than \(-74\,\hbox {dB}\) up to 10 MHz, while delivering the output current and voltage of 25 mA and 1.2 V, respectively.     

一种高电源抑制的基准源的设计

本文针对传统基准电压的低PSR以及低输出电压的问题,通过采用LDO与带隙基准的混合设计,并且采用BCD工艺,得到了一种可以输出较高参考电压的高PSR(电源抑制)带隙基准。此带隙基准的1.186 V输出电压在低频时PSR为-145 dB,在0～1 GHz频带内,最高PSR为-36 dB。在-50～150℃内,1.186 V基准的温漂为7.5 ppm/℃。     

一种用于LDO稳压器的共享预稳压电路

提出了一种用于LDO稳压器的共享预稳压电路.该共享预稳压电路中包含一个电源抑制减法电路以提高基准源的电源抑制,应用电流负反馈结构以降低基准源的温度系数和电源抑制随工艺阈值电压变化的敏感度,还可以降低LDO稳压器的输出噪声.仿真结果表明在阈值电压发生士20％变化的情况下,基准源的温度系数变化只有0.11×10-6/℃,电...     

A High Slew-Rate Push–Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement

A high slew-rate amplifier with push-pull output driving capability is proposed to enable an ultra-low quiescent current (Iq ~ 1muA) low-dropout (LDO) regulator with improved transient responses. The proposed amplifier eliminates the tradeoff between small Iq and large slew-rate that is imposed by the tail-current in conventional amplifier design. Push-pull output stage is introduced to enhance the output driving ability. Small dropout voltage (Vbo) with large-size pass transistor and ultra-low Iq can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed amplifier helps to improve stability of LDO regulators without using any on-chip and off-chip compensation capacitors. This is beneficial to chip-level power management requiring high-area efficiency. An LDO regulator with the proposed amplifier has been implemented in a 0.18- mum standard CMOS process and occupies 0.09 mm². The LDO regulator can deliver 50-mA load current at 1-V input and ~ 100-mV V_DO . It only consumes 1.2 muA Iq and is able to recover within ~ 4 mus even under the worst case scenario.     

A high-PSR transient-enhanced output-capacitorless CMOS low-dropout regulator for SoC applications

A transient-enhanced output-capacitorless CMOS low-dropout voltage regulator (LDO) with high power supply rejection (PSR) is introduced for system-on-chip applications. In order to reduce external pin count and device area and be amenable to full integration, the large external capacitor used in the classical LDO design is eliminated and replaced with a much smaller 5.7?pF on-chip capacitor. High-gain folded-cascode stage, wideband common source stage, voltage subtractor stage and transient-enhanced circuit are designed altogether to realise circuit compensation and achieve good frequency and transient performances. A current-sensing and transient-enhanced circuit is utilised to reduce transient voltage dips effectively and efficiently drive different kinds of load capacitances. The active chip area of the proposed regulator is only 200?×?280?µm². The simulation results under mixed-signal 0.18?µm 1P6M process show that this novel LDO's output voltage can recover within 1.7?µs (rising) and 2.41?µs (falling) under full load-current changes. The input voltage is ranged from 2 to 5?V for a load current 50?mA and an output voltage of 1.8?V. This novel LDO has wide unity-gain frequency stability and is stable for estimated equivalent parasitic capacitive loads from 0 to 100?pF. Moreover, it can achieve a PSR of ?78.5 and ?73?dB at 1 and 10?kHz, respectively.     

Less occupied and ultra-low noise LDO design

This paper presents a less-occupied and ultra-low noise LDO structure. This structure can achieve ultra-low noise performance without large filter capacitor by incorporating a capacitance amplifying circuit in the structure of LDO with pre-regulation. A large amount of chip area will be saved in this structure. A novel LDO in proposed structure is realized under SMIC 0.18 μm process. The experiment results show that proposed LDO structure can achieve a total output noise of 25.5 μV between 10 Hz and 1 kHz and 56.4 μV between 1 kHz and 1 MHz with a filter capacitor of 5pF. PSR is ?71.6 dB under low frequency until 49 kHz and at least ?65.7 dB under entire frequency range.     

A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier

Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.