基于构令流的RCSIMD体系结构研究

提出了基于构令流的多配多数据流(MCMD)的计算机体系结构并完成设计.通过重构,RCSIMD可支持SIMD和MIMD两种计算模型.RCSIMD中设计的两级配置策略,不但能够实现零配置延迟,而且还能在单周期内实现通信网络在一维和二维结构之间切换,极大地提高了结构的灵活性.多种算法的映射结果表明,RCSIMD体系结构适用于多媒体图像处理应用.在Charter 0.25μm 标准单元库下,RCSIMD的处理阵列的面积为7mm×7mm,时钟周期16ns.     

一种基于亚字并行的可重构阵列设计

设计了一种面向多媒体处理的8×8可重构处理阵列,并在该阵列基础上,对其粒度进行改进,提出了一种基于亚字并行的改进型可重构阵列设计思路.该设计根据图像处理中的算法的位宽特点,实现了一种数据的高位和低位可以同时运算的可重构阵列单元,有效提高数据的并行度,使得阵列的处理速度得到了显著的提高.在典型的图像处理中,这种改进型可重构阵列的处理能力较原来增加了一倍.     

基于高速图像数据Flash存储阵列无效块管理

针对高速图像数据FPGA大容量存储的需求,提出了两种基于高速并行化Flash大容量数据存储结构的无效块管理策略,并对比了在不同应用环境下,基于超级块地址映射的无效块管理及基于位索引的无效块管理的优缺点,列出了两种方式的数据无效块列表资源占用情况和存储容量损耗.通过多个工程项目的验证,这两种无效快管理策略各有所长,满足高速并行化存储Flash阵列的不同应用环境.     

探地雷达直达波衰减的Curvelet变换方法

针对探地雷达信号处理中直达波衰减问题,提出了一种基于Curvelet变换的直达波衰减方法.该方法首先将原始信号变换到Curvelet域,通过直达波在Curvelet域的分布特点,得到其Curvelet系数,并对其进行重构,最后在总信号中减去重构的直达波信号得到有效信号.在处理过程中,利用Curvelet域分尺度阈值处理方法同时可以滤除随机噪声.通过对实测数据的处理和分析,验证了该方法的可行性和有效性,并且证实了该方法与2-D连续小波变换方法相比具有占有存储少和计算速度快的特点.     

基于LS MPP的图像分块模板匹配并行算法

该文提出了一种新颖的在基于K元2-立方体网络的SIMD计算机上运行的图像分块模板匹配并行算法。该算法对于NN的图像、MM的模板和KK的处理元阵列(M K, N = BK, B 1), 可通过将图像分成BB个图像块的分块模板匹配来实现。与已知的各算法相比,该算法具有可处理比处理元阵列尺寸大的图像的优越性。     

完全搜索块匹配和图像空域滤波的可重构芯核

研究了一种用于图像领域的可重构微芯核结构,它可以支持运动估计算法中的完全搜索块匹配算法,同时也支持图像处理中的大部分空域模板滤波处理算法.在实现这两种算法时,也分别有一定的可重构性.该结构是一种并行处理结构,具有相当高的处理速度.文章提出的数据存储结构解决了并行处理数据与外部存储器的交换问题.     

基于ControlVAE的约束嵌入稠密时变阵列构建

在对探地雷达（Ground Penetrating Radar,GPR）数据进行三维建模与可视化分析过程中,其所依赖的三维时变阵列通常是由一维数据道或二维阵列间接生成的.由于采集到的数据往往比较稀疏,且存在不规则偏移,需要进行稠密处理,以获得高密度三维时变阵列.本文提出了一种基于可控变分自编码（Controllable Variational AutoEncoder,ControlVAE）的约束嵌入稠密时变阵列构建方法 .使用基于ControlVAE的时变数据重构网络,通过隐空间采样插值和深浅层特征信息的融合,生成接近真实分布的伪道数据来增加阵列密度.构建了基于尺度不变特征变换的数据配准模块,提取道间梯度特征与结构对称性特征,可以在时空域内完成数据配准.同时将浅层特征作为约束信息嵌入数据重构网络,以消除数据道偏移对阵列生成的影响.实验结果表明,本文方法仅使用单测线二维B-scan数据集即可重建稠密时变阵列,可以有效降低重构模型累积误差,提高面对复杂真实数据时的鲁棒性.     

基于ADSP—TS201S的二维DMA数据传输

针对高速信号处理系统中数据总线传榆的瓶颈问题,采用二维DMA方式进行外设高速缓存到DSP内核的数据块实时传输。对二维DMA控制币口状态寄存器组进行编程控制,结合FPGA与DSP链路接口设计,将存储区的数据块作为一个数据阵列进行传输,使DSP在DMA中断中获得数据。试验结果证明,二维DMA传输方式可解决高速外数据块的连续传输和处理问题,保证整个系统并行信号处理流水线的顺序执行,是一种解决数据总线传输瓶颈问题的实用方法。目前该技术已成功应用于某水声测量系统中。     

长度为2~n的多维离散傅里叶变换DFT(2~n;k)算法

本文论述了基于环结构的计算长度为2的整数幕多维离散傅里叶变换的算法.DFT(2~n;k)变换矩阵可换序成对应于互不相交核群K陪集的含有循环块的块结构矩阵.循环块又可进一步换序成具有相同块的块对角矩阵,而每一块是一维DFI,核CFT.     

粗粒度可重构结构的性能估计方法

在设计初期,估计粗粒度可重构结构的性能,对粗粒度可重构结构设计具有指导意义.在考虑局部数据存储器结构以及局部数据存储器与可重构阵列的接口结构的情况下,建立了粗粒度可重构结构的参数模型,使用改进的螺旋形绑定策略将应用算法DFG(Data Flow Graph)中的算子绑定到可重构阵列的处理单元上,提出了一种粗粒度可重构结构的性能估计方法.应用实例表明,在设计初期,该方法能得到周期精确的估计结果,有效地指导粗粒度可重构结构的设计.     

Automatic detection of conduction block based on time-frequencyanalysis of unipolar electrograms

It is commonly thought that lethal tachyarrhythmias, such as ventricular fibrillation (VF), are perpetuated by functional reentry, which occurs when an activation wave blocks and rotates around tissue that is excitable (i.e., functional block). Electrograms recorded near these regions typically contain two sequential deflections representing activation on either side of the block. By detecting these "double potentials," we hypothesize that functional block can be detected by a single electrode. METHODS: Unipolar electrograms were recorded from a 24 x 21 mapping array on the intact ventricular epicardium of five pigs during electrically-induced VF. The short time Fourier Transform (STFT) of each electrogram was analyzed to identify double potentials. To evaluate the performance of the STFT algorithm, conduction block was located in activation maps using a minimum conduction velocity criterion (10 cm/s) and then compared to the results of the STFT algorithm. RESULTS: The STFT algorithm detected conduction block with a sensitivity of 0.74 +/- 0.12 and a specificity of 0.99 +/- 0.00. CONCLUSION: We have developed an automated algorithm that can detect functional block during VF from a single electrode recording. Possible applications include fast, objective identification of block in mapping data and realtime localization of reentrant substrates using mapping catheters.     

基于无冲突地址生成的高性能FFT处理器设计

提出一种基于存储器交织架构的FFT处理器设计方法,并且针对基-8FFT提出一种无冲突地址生成算法,数据按帧进行操作。每个存储器均划分为8个独立的存储体,通过对循环移位寄存器译码,蝶式运算单元并行无冲突读写操作数,8通道输入数据进行并行的复数乘法运算。每级运算引入完全流水,减少了运算的时钟周期开销,同时推导出局部流水线设计必须满足的不等式条件。输入、输出存储器采用乒乓操作,按帧轮换,FFT运算连续输入、输出,采样频率与系统工作频率一致,具有很好的实时性,运算精度通过块浮点得到保证。该设计方法可以扩展至基-16FFT处理器设计。     

A multilevel matrix decomposition algorithm for analyzingscattering from large structures

A multilevel algorithm is presented for analyzing scattering from electrically large surfaces. The algorithm accelerates the iterative solution of integral equations that arise in computational electromagnetics. The algorithm permits a fast matrix-vector multiplication by decomposing the traditional method of moment matrix into a large number of blocks, with each describing the interaction between distant scatterers. The multiplication of each block by a trial solution vector is executed using a multilevel scheme that resembles a fast Fourier transform (FFT) and that only relies on well-known algebraic techniques. The computational complexity and the memory requirements of the proposed algorithm are O(N log² N)     

A New Overlap Save Algorithm for Fast Block Convolution and Its Implementation Using FFT

Convolution of data with a long-tap filter is often implemented by overlap save algorithm (OSA) using fast Fourier transform (FFT). But there are some redundant computations in the traditional OSA because the FFT is applied to the overlapped data (concatenation of previous block and the current block) while the DFT computations are recursive. In this paper, we first analyze the redundancy by decomposing the OSA into two processes related to the previous and current block. Then we eliminate the redundant computations by introducing a new transform which is applied only to the current data, not to the overall overlapped data. Hence the size of transform is reduced by half compared to the traditional OSA. The new transform is in the form of DFT and it can be implemented by defining a new butterfly structure. However we implement it by a cascade of twiddle factor and conventional FFT in this paper, in order to use the FFT libraries in PC and DSP. The computational complexity in this case is analyzed and compared with the existing methods. In the experiment, the proposed method is applied to several block convolutions and partitioned-block convolutions. The CPU time is reduced more than expected from the arithmetic analysis, which implies that the reduced transform size gives additional advantage in data manipulation.     

FRACTAL BLOCK CODING IN RESIDUE DOMAIN

A new block-based fractal image coding algorithm called Fractal Block Coding in Residue Domain (FBCRD) is proposed. In basic Fractal Block Coding (FBC) algorithm, each block (called range block) is encoded by an affine mapping from a domain block within the same image to itself. The decoder uses the parameters of these mappings to synthesize the reconstructed image through an iterative procedure. FBCRD is a modification of basic FBC. In FBCRD, range blocks and domain blocks are all residue blocks subtracted from their block means and both the parameters of affine mappings and block means are coded. This modification leads to fewer iterations at the decoder. An optimized decoding strategy is also introduced which reduces total decoding time by more than half of that of basic FBC. This improvement is favorable for real time implementation of fractal image compression. Supported in Part by the Defence Preresearch Foundation, the National Science Foundation of Guangdong Prooince and the National “Chinbing” Project     

一种降低FBMC-OQAM系统PAPR的低复杂度选择性映射算法

滤波器组多载波(FBMC)是第五代蜂窝网络无线接入技术重点考虑的对象之一,然而其存在较高的峰均功率比(PAPR).通过分析FBMC-OQAM信号的重叠特性和信号功率分布特点,将传统选择性映射(SLM)方法加以改进,提出了一种比色散选择性映射(DSLM)方法更优的低复杂度色散选择性映射(LD-SLM)方法.LD-SLM方法用备选旋转矢量将当前数据块信号旋转,通过计算在当前信号周期[T,3T]区间内信号的PAPR来选取最优旋转矢量,并更新当前数据块信号,接着对下一个数据块信号进行同样的优化,直至所有的数据块都被优化.通过比较算法复杂度可知,LD-SLM算法相比DSLM算法降低了50％,仿真实验表明LD-SLM方法能有效降低FBMC-OQAM系统的PAPR.     

16点基4-FFT芯片设计技术研究

FFT算法是高速实时信号处理的关键算法之一,在很多领域有广泛应用。文中采用了基-4,按时间抽取FFT算法,完成了16点,32bit位长,定点复数FFT的设计。基-4蝶形单元中采用32位Booth算法乘法器,并使用3级流水线设计,并行的处理四路输入数据,极大地提高了FFT的处理速度。本设计划分为多个功能模块,全部采用Verilog HDL语言描述,并且通过仿真验证。     

一种实时自适应脉内特征分析方法

阐述了重构相位的高阶差分和基16FFT实时脉内特征分析算法原理,提出利用多次相位高阶差分方法识别脉内调频和相位编码两种调制类型,提出分段进行4096点基16FET频谱分析的设计思想,保证了线性调频信号脉内特征分析的实时性和精度要求。利用相位高阶差分包络板值检测方法提取信号的突变信息,达到实时提取相位编码信号的脉内调制信息的目的,理论分析了算法的实现过程并给出了脉内分析的流程图。通过仿真和在某大型电子对抗系统上的成功应用,证明了该方法在低信噪比环境下的有效性。     

New block filtered-X LMS algorithms for active noise control systems

New block formulations for an active noise control (ANC) system using only convolution machines are presented. The proposed approaches are different from conventional block least-mean-square (LMS) algorithms that use both convolution and cross-correlation machines. The block implementation is also applied to the filtering of the reference signal by the secondary-path estimate. In addition to the use of the fast Fourier transform (FFT), the fast Hartley transform (FHT) is used to develop transform-domain ANC structures for reducing computational complexity. In the proposed approach, some FFT and FHT blocks are removed to obtain an additional reduction of the computational burden resulting in the reduced-structure of FFT-based block filtered-X LMS (FBFXLMS) and FHT-based block filtered-X LMS (HBFXLMS) algorithms. The computational complexities of these new ANC structures are evaluated.     

基于FPGA的专用信号处理器设计

用可编程门阵列(FPGA)实现了一个专用信号处理器,它以快速傅里叶变换(FFT)为核心工作单元,对四路零中频雷达回波依次进行去除直流分量、数据加窗、FFT、目标信号选大和相位参考信号检测等处理。各处理单元流水操作,保证了处理速度,提高了资源的利用效率。FFT算法为输入顺序输出位反序的D IT基2算法,采用递归结构实现,硬件共享设计节省了资源;同时,处理过程中采用块浮点算法,兼顾了定点的高速度与浮点的高精度;并对FFT结果进行了误差分析,给出了定点与块浮点两种算法时的均方误差上限。最后对整个设计进行了仿真验证,结果表明用FPGA实现专用信号处理器满足系统要求。