基于UPC1909的有源箝位软开关变换器

在常规的硬开关电路中,由于变压器漏感及寄生电容的影响,常常在开关转换瞬间会产生很高的电压尖峰。本文采用有源箝位反激式变换器电路,实现了零电压零电流(ZVZCS)软开关变换,使电压尖峰得到了抑制。该电路成功地应用了UPCI909控制芯片,简化了传统的驱动电路。实验结果表明,主开关管两端电压被箝位在一定数值,实现了零电压零电流开关,效率达到90％。     

基于肖特基栅共振隧穿三极管的器件模拟与实验分析

通过流片,制作出肖特基栅共振隧穿三极管（SGRTT） .根据ATLAS软件的模拟发现,当发射极接地,集电极接外加偏压时,栅极电压对于SGRTT的电流起到明显的控制作用.当集电极接地,栅极电压会主要影响峰值电压,其原因是栅极电压和发射极、集电极的电场分布将会改变耗尽区的分布.实验测试结果对这种现象也予以证实.     

基于肖特基栅共振隧穿三极管的器件模拟与实验分析

通过流片,制作出肖特基栅共振隧穿三极管(SGRTT).根据ATLAS软件的模拟发现,当发射极接地, 集电极接外加偏压时,栅极电压对于SGRTT的电流起到明显的控制作用.当集电极接地,栅极电压会主要影响峰值电压,其原因是栅极电压和发射极、集电极的电场分布将会改变耗尽区的分布.实验测试结果对这种现象也予以证实.     

1986年南京大学硕士学位研究生入学试题及题解

试题名称:电子线路一、一单管放大电路如图1所示,三极管BG为?中频区?忽略不计.1.求三极管集电极静态电压和静态电流;2.求中频区该放大电路的输入阻抗?和输出阻抗R_0;3.求中频区电压放大倍数K_v;4.求低频截止频率f_?;5.如果要求放大电路的高频截止频率f_h=     

三极管在振荡电路中的另类接法

通过实验以8050和8550三极管为研究对象,测试了NPN型和PNP型三极管的不同接法。通过数据分析,在振荡电路中,当三极管工作在开关状态时,不论NPN型还是PNP型三极管其集电极和发射极可以互换,并且PNP型三极管只有在有基极电流的情况才能处于饱和导通状态,纠正了许多教材中关于集电极和发射极绝对不可以互换的错误观点,提供了三极管在振荡电路及其他作为开关使用的电路新的接法。     

CATV放大器工作原理及应用(5)放大器的核心放大电路

(上接2002年第23期) 放大器是由晶体三极管或场效应管等具有正向受控作用的器件以及输入信号源、负载电阻、直流电源和偏置电阻等部分组成.最基本的放大电路有共发射极(共源极)、共基极(共栅极)和共集电极(共漏极)3种类型,其中共基极电路的电流增益和共集电极的电压增益都小于1,只有共发射极电路的电压增益和电流增益都较大,所以要求有较大增益的放大器都主要由共发射极电路组成,共基极电路输入阻抗较小,输出阻抗很大;共集电极电路输入阻抗很大,输出阻抗很小,它们可用于阻抗匹配和级间隔离,共集电极电路又称射极跟随器,在放大器电路中用得较多.     

放大器的核心放大电路

(上接 2 0 0 2年第 2 3期 )放大器是由晶体三极管或场效应管等具有正向受控作用的器件以及输入信号源、负载电阻、直流电源和偏置电阻等部分组成。最基本的放大电路有共发射极(共源极 )、共基极 (共栅极 )和共集电极 (共漏极 ) 3种类型 ,其中共基极电路的电流增益和共集电极的电压增益都小于 1,只有共发射极电路的电压增益和电流增益都较大 ,所以要求有较大增益的放大器都主要由共发射极电路组成 ,共基极电路输入阻抗较小 ,输出阻抗很大 ;共集电极电路输入阻抗很大 ,输出阻抗很小 ,它们可用于阻抗匹配和级间隔离 ,共集电极电路又称射极跟随…     

精确实用的电压-频率转换电路

<正> 本文介绍的电压-频率转换电路,不仅是一种实用而精确的电路,而且还具有转换频率的上下限控制电路。它用于控制电机转速时,可以限制电机的最低转速和最高转速。从而有效地防止了电机的超高速和过低速的运行。该电路可以实现无级调速,且转换精度高,抗干扰性能强,测试简单。 该电路如图所示。以三极管U1和双向门IC12为核心的电路是转换频率设置电路。三极管U1是用来控制双向门IC12的。当从电阻R1输入一个低电平时,三极管U1截止,其集电极输出高电平,使双向门IC12导通,通过S按     

利用关键测试点数据检修彩电各部分电路故障

无论是普通的遥控彩电，还是多制式大屏幕彩电，在它们的功能电路中均有集成块和三极管等器件。一般而言，通过测试集成块的引脚电压、电阻值以及三极管的各极电压、电阻值，有可能知道各个单元电路是否有问题，进而判断故障原因、找出故障发生的部位及故障元器件等。１开关电源１．１开关电源的关键测试点一是开关管集电极；二是开关电源各电压输出端；三是开／待机接口末端晶体管集电极或发射极。１．２各测试点电压能说明的问题１）开关管集电极电压开关管的集电极电压由桥式整流滤波电路对市电交流２２０V整流滤波而得。因各地市电在交…     

晶体三极管β值的测试方法

β代表晶体三极管共发射极直流电流放大系数,β=I_c/I-b。I_c是集电极电流,I_b是基极电流。 当I_c和V_(ce)(集电极-发射极电压)取值不同时β值也略有不同。因此手册上所规定的β值都是在一定的I_c和V_(ce)数值下测得。测试时按图1所示的电路进行。先调节E_c使V_(ce)为规定值,再调节E_b使I_c为规定值。     

RBSOA characterization of GTO devices

GTO devices are characterized using a nondestructive RBSOA (reverse bias safe operating area) tester. Breakdown phenomena observed in GTO testing are very much different from those of a BJT. Explanation of the cause of the loss of device voltage blocking capability during turn-off is given     

1200-V 5.2-mΩ·cm2 4H-SiC BJTs With a High Common-Emitter Current Gain

This letter presents fabrication of a power 4H-SiC bipolar junction transistor (BJT) with a high open-base breakdown voltage BV_CEO ap 1200 V, a low specific on-resistance R _{SP_ON} ap 5.2 mOmegamiddotcm², and a high common-emitter current gain beta ap 60. The high gain of the BJT is attributed to reduced surface recombination that has been obtained using passivation by thermal silicon dioxide grown in nitrous oxide (N₂O) ambient. Reference BJTs with passivation by conventional dry thermal oxidation show a clearly lower current gain and a more pronounced emitter-size effect. BJTs with junction termination by a guard-ring-assisted junction-termination extension (JTE) show about 400 V higher breakdown voltage compared with BJTs with a conventional JTE.     

一种低失调高压大电流集成运算放大器

基于结型场效应晶体管(JFET)和双极型晶体管(BJT)兼容工艺,设计了一种低失调高压大电流集成运算放大器。电路输入级采用p沟道JFET (p-JFET)差分对共源共栅结构;中间级以BJT作为放大管,采用复合有源负载结构;输出级采用复合npn达林顿管阵列,与常规推挽输出结构相比,在输出相同电流的情况下,节省了大量芯片面积。基于Cadence Spectre软件对该运算放大器电路进行了仿真分析和优化设计,在±35 V电源供电下,最小负载电阻为6Ω时的电压增益为95 dB,输入失调电压为0.224 5 mV,输入偏置电流为31.34 pA,输入失调电流为3.3 pA,单位增益带宽为9.6 MHz,具有输出9 A峰值大电流能力。     

4H-SiC power bipolar junction transistor with a very low specific ON-resistance of 2.9 m/spl Omega//spl middot/cm/sup 2/

This letter reports a newly achieved best result on the specific ON-resistance (R/sub SP/spl I.bar/ON/) of power 4H-SiC bipolar junction transistors (BJTs). A 4H-SiC BJT based on a 12-/spl mu/m drift layer shows a record-low specific-ON resistance of only 2.9 m/spl Omega//spl middot/cm/sup 2/, with an open-base collector-to-emitter blocking voltage (V/sub ceo/) of 757 V, and a current gain of 18.8. The active area of this 4H-SiC BJT is 0.61 mm/sup 2/, and it has a fully interdigitated design. This high-performance 4H-SiC BJT conducts up to 5.24 A at a forward voltage drop of V/sub CE/=2.5 V, corresponding to a low R/sub SP-ON/ of 2.9 m/spl Omega//spl middot/cm/sup 2/ up to J/sub c/=859 A/cm/sup 2/. This is the lowest specific ON-resistance ever reported for high-power 4H-SiC BJTs.     

A curvature calibrated bandgap reference with base-emitter current compensating in a 0.13/tm CMOS process

In bandgap References,the effect caused by the input offset of the operational amplifier can be effectively reduced by the utilization of cascade bipolar junction transistors(BJTs).But in modern CMOS logic processes,due to the small value of β,the base-emitter path of BJTs has a significant streaming effect on the collector current,which leads to a large temperature drift for the reference voltage.To solve this problem,a base-emitter current compensating technique is proposed in a cascade BJT bandgap reference structure to calibrate the curvature of the output voltage to temperature.Experimental results based on the 0.13 μm logic CMOS process show that the reference voltage is 1.238V and the temperature coefficient is 6.2 ppm/℃ within the range of-40 to 125 ℃.     

微纳级双极晶体管的热耗散研究

对于双极性晶体管,由于自身存在的自加热现象,严重地影响着器件的特性。基于热电流方程、泊松方程及电流密度方程,在二维器件仿真环境下,进行了微纳级小尺寸npn双极性晶体管热现象的器件物理特性分析。重点研究了器件的集电极电流IC与晶格温度T的因变关系。研究结果显示,随着IC的增加,器件的晶格温度逐渐升高,VCE保持在3.0V、VBE达到最大值0.735V时,随器件晶格温度的升高VBE将减小。最后,笔者给出了描述晶体管温变关系的三维曲线。     

A new type of transistor: CBT

A transistor called the channel-base transistor (CBT), which is constructed by making channels through the base of the conventional bipolar junction transistors (BJTs), is proposed. In principle, a CBT can be treated as a combination of a BJT and a normally-off junction-type field-effect transistor (E-JFET). Silicon planer CBTs have been fabricated with BJTs on the same wafer for comparison. The electrical characteristics of CBTs are similar to those of a conventional BJTs, but the variations of current gain with temperature and emitter current in CBTs are much less than those in the BJTs. In addition, the magnitude of current gain of CBTs is higher than that of comparable BJTs. Transistor-transistor-logic (TTL) NAND-gate ICs implemented with CBTs have been fabricated. The temperature variations of parameters in CBT ICs are less than those in BJT ICs. Experiments have shown that silicon CBT discrete devices and ICs can be used over a wide range of temperatures from -60°C to 200°C. Experimental and theoretical analysis results for CBTs are presented     

Modulating the bipolar junction transistor subjected to neutronirradiation for integrated circuit simulation

Bipolar junction transistors (BJTs) are susceptible to particle bombardment in radiative environment. A model that is capable of predicting the performance of a BJT subjected to neutron irradiation and that is suitable for SPICE circuit simulation is presented. It is shown that neutron irradiation affects the emitter-base space-charge region capacitance slightly but strongly influences the forward-active current gain. Results calculated from the present model compared favorably with measured dependencies available in the literature. The model was implemented in SPICE, and the performance of a BJT differential amplifier was simulated     

Fabrication and Characterization of High-Current-Gain 4H-SiC Bipolar Junction Transistors

This paper reports on newly developed high-performance 4H-SiC bipolar junction transistors (BJT) with improved current gain and power handling capabilities based on an intentionally designed continuously grown 4H-SiC BJT wafer. The measured dc common-emitter current gain is as high as 70, the specific on -state resistance $(R_{{rm SP}hbox{-}{rm ON}})$ is as low as 3.0 $hbox{m}Omegacdothbox{cm}^{2}$, and the open-base breakdown voltage $(V_{rm CEO})$ reaches 1750 V. Large-area 4H-SiC BJTs with a footprint of 4.1 $times$ 4.1 mm have been successfully packaged into a high-gain $(beta = hbox{50.8})$ high-power (80 A $times$ 700 V) all-SiC copack and evaluated at high temperature up to 250 $^{circ}hbox{C}$. Small 4H-SiC BJTs have been stress tested under a continuous collector current density of 100 $hbox{A}/hbox{cm}^{2}$ for 24 h and, for the first time, have shown no obvious forward voltage drift and no current gain degradation. Numerical simulations and experimental results have confirmed that simultaneous high current gain and high open-base breakdown voltage could be achieved in 4H-SiC BJTs.      

High-Current-Gain SiC BJTs With Regrown Extrinsic Base and Etched JTE

This paper describes successful fabrication of 4H-SiC bipolar junction transistors (BJTs) with a regrown extrinsic base layer and an etched junction termination extension (JTE). Large-area 4H-SiC BJTs measuring 1.8 $times$ 1.8 mm (with an active area of 3.24 $hbox{mm}^{2}$) showed a common emitter current gain $beta$ of 42, specific on-resistance $R_{{rm SP}_{rm ON}}$ of 9 $hbox{m}Omegacdothbox{cm}^{2}$, and open-base breakdown voltage $hbox{BV}_{rm CEO}$ of 1.75 kV at room temperature. The key to successful fabrication of high-current-gain SiC BJTs with a regrown extrinsic base is efficient removal of the $hbox{p}^{+}$ regrown layer from the surface of the emitter–base junction. The BJT with $hbox{p}^{+}$ regrown layer has the advantage of lower base contact resistivity and current gain that is less sensitive to the distance between the emitter edge and the base contact, compared to a BJT with ion-implanted base. Fabrication of BJTs without ion implantation means less lifetime-reducing defects, and in addition, the surface morphology is improved since high-temperature annealing becomes unnecessary. BJTs with flat-surface junction termination that combine etched regrown layers show about 250 V higher breakdown voltage than BJTs with only etched flat-surface JTE.