MPEG Reconfigurable Video Coding: From specification to a reconfigurable implementation

This paper demonstrates that it is possible to produce automatic, reconfigurable, and portable implementations of multimedia decoders onto platforms with the help of the MPEG Reconfigurable Video Coding (RVC) standard. MPEG RVC is a new formalism standardized by the MPEG consortium used to specify multimedia decoders. It produces visual representations of decoder reference software, with the help of graphs that connect several coding tools from MPEG standards. The approach developed in this paper draws on Dataflow Process Networks to produce a Minimal and Canonical Representation (MCR) of MPEG RVC specifications. The MCR makes it possible to form automatic and reconfigurable implementations of decoders which can match any actual platforms. The contribution is demonstrated on one case study where a generic decoder needs to process a multimedia content with the help of the RVC specification of the decoder required to process it. The overall approach is tested on two decoders from MPEG, namely MPEG-4 part 2 Simple Profile and MPEG-4 part 10 Constrained Baseline Profile. The results validate the following benefits on the MCR of decoders: compact representation, low overhead induced by its compilation, reconfiguration and multi-core abilities.     

Reconfigurable video coding on multicore

The current monolithic and lengthy scheme behind the standardization and the design of new video coding standards is becoming inappropriate to satisfy the dynamism and changing needs of the video coding community. Such scheme and specification formalism does not allow the clear commonalities between the different codecs to be shown, at the level of the specification nor at the level of the implementation. Such a problem is one of the main reasons for the typically long interval elapsing between the time a new idea is validated until it is implemented in consumer products as part of a worldwide standard. The analysis of this problem originated a new standard initiative within the International Organization for Standardization (ISO)/International Electrotechnical Commission (IEC) Moving Pictures Experts Group (MPEG) committee, namely Reconfigurable Video Coding (RVC). The main idea is to develop a video coding standard that overcomes many shortcomings of the current standardization and specification process by updating and progressively incrementing a modular library of components. As the name implies, flexibility and reconfigurability are new attractive features of the RVC standard. Besides allowing for the definition of new codec algorithms, such features, as well as the dataflow-based specification formalism, open the way to define video coding standards that expressly target implementations on platforms with multiple cores. This article provides an overview of the main objectives of the new RVC standard, with an emphasis on the features that enable efficient implementation on platforms with multiple cores. A brief introduction to the methodologies that efficiently map RVC codec specifications to multicore platforms is accompanied with an example of the possible breakthroughs that are expected to occur in the design and deployment of multimedia services on multicore platforms.     

Reconfigurable media coding: An overview

This paper provides an overview of the rationale of the Reconfigurable Media Coding framework developed by MPEG standardization committee to overcome the limits of traditional ways of providing decoder specifications. Such framework is an extension of the Reconfigurable Video coding framework now encompassing also 3D Graphics coding standard. The idea of this approach is to specify decoders using an actor dataflow based representation consisting of self-contained processing units (coding tools) connected altogether and communicating by explicitly exchanging data. Such representation provides a specification for which several properties of the algorithms interesting for codec implementations are explicitly exposed and can be used for exploring different implementation objectives.     

Overview of the MPEG Reconfigurable Video Coding Framework

Video coding technology in the last 20 years has evolved producing a variety of different and complex algorithms and coding standards. So far the specification of such standards, and of the algorithms that build them, has been done case by case providing monolithic textual and reference software specifications in different forms and programming languages. However, very little attention has been given to provide a specification formalism that explicitly presents common components between standards, and the incremental modifications of such monolithic standards. The MPEG Reconfigurable Video Coding (RVC) framework is a new ISO standard currently under its final stage of standardization, aiming at providing video codec specifications at the level of library components instead of monolithic algorithms. The new concept is to be able to specify a decoder of an existing standard or a completely new configuration that may better satisfy application-specific constraints by selecting standard components from a library of standard coding algorithms. The possibility of dynamic configuration and reconfiguration of codecs also requires new methodologies and new tools for describing the new bitstream syntaxes and the parsers of such new codecs. The RVC framework is based on the usage of a new actor/ dataflow oriented language called CAL for the specification of the standard library and instantiation of the RVC decoder model. This language has been specifically designed for modeling complex signal processing systems. CAL dataflow models expose the intrinsic concurrency of the algorithms by employing the notions of actor programming and dataflow. The paper gives an overview of the concepts and technologies building the standard RVC framework and the non standard tools supporting the RVC model from the instantiation and simulation of the CAL model to software and/or hardware code synthesis.     

Techniques for Random Masking in Hardware

A new technique for Boolean random masking of the logic and operation in terms of nand logic gates is proposed and applied for masking the integer addition. The new technique can be used for masking arbitrary cryptographic functions and is more efficient than previously known techniques, recently applied to the Advanced Encryption Standard (AES). New techniques for the conversions from Boolean to arithmetic random masking and vice versa are also developed. They are hardware oriented and do not require additional random bits. Unlike the previous, software-oriented techniques showing a substantial difference in the complexity of the two conversions, they have a comparable complexity being about the same as that of one integer addition only. All the techniques proposed are in theory secure against the first-order differential power analysis on the logic gate level. They can be applied in hardware implementations of various cryptographic functions, including AES, (keyed) SHA-1, IDEA, and RC6     

Secure MQ coder: An efficient way to protect JPEG 2000 images in wireless multimedia sensor networks

This paper presents a secure MQ coder (SMQ) for efficient selective encryption of JPEG 2000 images. Being different from existing schemes where encryption overhead is proportional to the size of plain image, SMQ only selectively encrypts tiny and constant volume of data in JPEG 2000 coding regardless of image size. It is extremely fast and suitable for protecting JPEG 2000 images in wireless multimedia sensor networks (WMSNs). Theoretical analysis and experimental results show that SMQ can achieve a balance between security and efficiency, while keeping comparable compression performance and energy consumption with standard JPEG 2000 coding.     

Methods to explore design space for MPEG RMC codec specifications

The recent MPEG Reconfigurable Media Coding (RMC) standard aims at defining media processing specifications (e.g. video codecs) in a form that abstracts from the implementation platform, but at the same time is an appropriate starting point for implementation on specific targets. To this end, the RMC framework has standardized both an asynchronous dataflow model of computation and an associated specification language. Either are providing the formalism and the theoretical foundation for multimedia specifications. Even though these specifications are abstract and platform-independent the new approach of developing implementations from such initial specifications presents obvious advantages over the approaches based on classical sequential specifications. The advantages appear particularly appealing when targeting the current and emerging homogeneous and heterogeneous manycore or multicore processing platforms. These highly parallel computing machines are gradually replacing single-core processors, particularly when the system design aims at reducing power dissipation or at increasing throughput. However, a straightforward mapping of an abstract dataflow specification onto a concurrent and heterogeneous platform does often not produce an efficient result. Before an abstract specification can be translated into an efficient implementation in software and hardware, the dataflow networks need to be partitioned and then mapped to individual processing elements. Moreover, system performance requirements need to be accounted for in the design optimization process. This paper discusses the state of the art of the combinatorial problems that need to be faced at this design space exploration step. Some recent developments and experimental results for image and video coding applications are illustrated. Both well-known and novel heuristics for problems such as mapping, scheduling and buffer minimization are investigated in the specific context of exploring the design space of dataflow program implementations.     

运营商业务平台安全域防护策略及安全基线设计

面对日益增大的网络安全威胁,电信运营商需要提高业务平台的安全防护能力.结合电信运营商业务平台的系统现状,在对各类业务平台进行安全分级的基础上,规范划分不同网络结构业务平台的安全域,并针对不同安全等级平台设计合理可控的安全防护策略和安全基线,使业务平台形成安全、清晰、便于管控的网络布局和系统架构.     

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications

A heterogeneous multicore system-on-chip (SoC) has been developed for high-definition (HD) multimedia applications that require secure DRM (digital rights management). The SoC integrates three types of processors: two specific-purpose accelerators for cipher and high-resolution video decoding; one general-purpose accelerator (MX); and three CPUs. This is how our SoC achieves high performance and low power consumption with hardware customized for video processing applications that process a large amount of data. To achieve secure data control, hardware memory management and software system virtualization are adopted. The security of the system is the result of the cooperation between the hardware and software on the system. Furthermore, a highly tamper-resistant system is provided on our SiP (System in a package), through DDR2 SDRAMs and a flash memory that contain confidential information in one package. This secure multimedia processor provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery. The SoC was implemented in a 90 nm generic CMOS technology.      

智能电视规范概述

智能电视作为彩电行业的新兴技术,是未来彩电行业产业结构调整和转型升级的主要方向。根据奥维咨询(AVC)预测,2013年智能电视渗透率达到47%,到2020年智能电视渗透率达到93%。通过介绍中国电子视像行业协会制定的智能电视机总规范、智能电视操作系统技术规范、平台及第三方应用接口技术规范、人机交互技术规范、智能电视应用商店技术规范、智能电视系统安全技术规范等智能电视系列规范,旨在对制定智能电视国家标准有一定借鉴意义。     

A flexible middleware for multimedia communication: design,implementation, and experience

Distributed multimedia applications require a variety of communication services. These services and different application requirements have to be provided and supported within: (1) end-systems in an efficient and integrated manner, combining the precise specification of quality-of-service (QoS) requirements, application interfaces, multicast support, and security features and (2) the network. The Da CaPo++ system presented in this paper provides an efficient end-system middleware for multimedia applications, capable of handling various types of applications in a modular fashion. Application needs and communication demands are specified by values in terms of QoS attributes and functional properties, such as encryption requirements or multicast support. Da CaPo++ automatically configures suitable communication protocols, provides for an efficient runtime support, and offers an easy-to-use, object-oriented application programming interface. While its applicability to real-life applications was shown by prototype implementations, performance evaluations have been carried out yielding practical experiences and numerical results     

基于QoS策略的视频监控系统的设计

网络化视频监控系统是集网络、通信以及视频编解码等多项技术的整合系统。文章先提出了网络化视频监控系统的系统结构，接着重点介绍了网络化视频监控系统中如何有效的应用QoS策略来优化多媒体流的传输和视频的质量。     

Rational function distribution in computer system architectures: key to stable and secure platforms

Many problems faced in implementing computer-based system applications are related to the deployment of commercially available general-purpose computer system platforms. In the provisioning application software products and services, the platforms have often proven to be the most unreliable, costly, and risk-laden system element. There are historical reasons for the current problems that must be understood in order to map out a path for a future where stable and secure platforms can be provided as reliable commercially available system elements. This paper extends a model of function distribution between various hardware and software levels from a previously published result (Lawson, "Function distribution in computer system architectures," presented at the 3rd Annu. Symp. Computer Architecture, 1976). After a review of the revised model, related principles are "reapplied" to the current situation. Alternative paths that can lead to stable and secure computer platforms via the rational distribution of functions are presented. Finally, the need for as well as the potential impact of autonomic computing is described.     

Energy efficient distributed steganography for secure communication in wireless multimedia sensor networks

A secure communication mechanism is necessary in the applications of Wireless Multimedia Sensor Networks (WMSNs), which is more vulnerable to security attacks due to the presence of multimedia data. Additionally, given the limited technological resources (in term of energy, computation, bandwidth, and storage) of sensor nodes, security and privacy policies have to be combined with energy-aware algorithms and distributed processing of multimedia contents in WMSNs. To solve these problems in this paper, an energy efficient distributed steganography scheme, which combines steganography technique with the concept of distributed computing, is proposed for secure communication in WMSNs. The simulation results show that the proposed method can achieve considerable energy efficiency while assuring the communication security simultaneously.     

密码算法的研究综述

对密码算法进行了概述和分类,并在此基础上论述了密码算法的现状。在哈希函数方面,研究了在MD5和SHA-1被破解后HMAC的健壮性是否变化;在对称密钥算法方面,论述了AES的特点并将其与DES,3DES及IDEA进行了比较;在非对称密钥算法方面,比较了RSA,DSA和ElGamal,并且详细说明了ECC。最后对密码算法的发展进行了展望。     

WSNs中基于FPGA的AES-ECC新型加密系统

针对无线传感器网络的特点,提出一种适于FPGA实现的改进的AES-ECC混合加密系统。本方案采用AES模块对数据进行加密,用SHA-1加密算法处理数据得到数据摘要,用ECC加密算法实现对摘要的签名和对AES私钥的加密。各个算法模块采用并行执行的处理方式以提高运算效率。方案优化了AES加密模块的设计,在占用相对较少逻辑资源的同时提高了系统吞吐率,通过优化ECC乘法单元的设计,提高了数字签名生成和认证的速度,完全满足了无线传感器网络对于稳定性、功耗以及处理速度的要求,给数据传输的安全性提供了高强度的保障。     

基于EPON网的AES加密电路设计

EPON网是基于千兆以太网的无源光网络技术,是光纤接入网的重要解决方案之一,具有良好的市场发展空间。随着广电网络技术的发展,信息安全的重要性日益增加,加密技术也越来越受到关注。AES算法作为现在的主流加密手段,是密码学中的高级加密标准,对它进行学习和运用具有十分重要的现实意义。讨论EPON系统下行传输存在的安全问题,并简单介绍高级加密算法（AES）在EPON系统内的实现方式,其中主要涉及AES原理的分析以及AES算法的硬件实现和功能仿真。     

AES算法的密码分析与快速实现

高级加密标准(AES)确定分组密码Rijndael为其算法,取代厂泛使用了20多年的数据加密标准(DES),该算法将在各行业各部门获得广泛的应用.文章以DES为参照对象,阐述了Rijndael算法的设计特色,介绍了AES在密码分析方面国内外已有的一些理论分析成果,描述了AES算法采用软件和硬件的快速实现方案.     

Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box

Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, wherein hardware designs for FPGAs and standard cells received particular attention. In this paper we present a comprehensive study of different standard-cell implementations of the AES S-box with respect to timing (i.e. critical path), silicon area, power consumption, and combinations of these cost metrics. We examine implementations which exploit the mathematical properties of the AES S-box, constructions based on hardware look-up tables, and dedicated low-power solutions. Our results show that the timing, area, and power properties of the different S-box realizations can vary by up to almost an order of magnitude. In terms of area and area-delay product, the best choice are implementations which calculate the S-box output. On the other hand, the hardware look-up solutions are characterized by the shortest critical path. The dedicated low-power implementations do not only reduce power consumption by a large degree, but they also show good timing properties and offer the best power-delay and power-area product, respectively.