Effects of hot-carrier trapping in n- and p-channel MOSFET's

Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.     

Surface states and 1/f noise in MOS transistors

Surface-state density in n-channel MOS transistors operating in the inversion mode has been determined from the channel conductance and related to 1/fnoise in these devices. It has been found that the noise is proportional to the surface-state density at the Fermi level. The surface orientation and temperature affect the noise output only indirectly, through their influence on the surface-state density and the position of the Fermi level at the surface.     

Reoxidized nitrided oxides (RNO) for latent ESD-resistant MOSFETdielectrics

n-channel MOSFETs with reoxidized nitrided oxides (RNOs) are compared to conventional oxides with respect to their susceptibility to latent damage from electrostatic discharge (ESD) and ESD-like events. It is shown, using both ESD events and simulated ESD events by snapback, that the RNO devices have substantially better resistance to latent damage from such events. The increased resistance is explained by the robustness of the nitrided oxides both to interface state generation and to oxide trap creation by hot-hole injection. It is concluded that, along with hot-carrier resistance, the RNO robustness to latent ESD damage is another advantage of this technology     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

Hot-hole-induced dielectric breakdown in LDMOS transistors

A novel failure mechanism in an n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor biased in the saturation mode is investigated. A correlation between time-to-breakdown and hot hole gate current is established and the static safe operating area (SOA), limited by hot-hole-induced dielectric breakdown, is defined. A method based on the evaluation of the time integral of an "effective" hot-hole gate current is proposed which allows us to estimate the time-to-fail of the device operating in any dynamic (periodic) mode, beyond its static SOA. The prebreakdown degradation of some electrical parameters, attributed to hot hole injection into the gate oxide, is also discussed.     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Relationship between hot-electrons/Holes and degradation of p- and n-channel MOSFET's

The relationship between hot electrons and holes and the degradation of p- and n-channel MOSFET's is clarified by experimentally determining where along the channel the SiO2is most affected by each type of carrier. Transconductance degradation is found to be caused by hot-hole injection in pMOSFET's, and by hot-electron injection in nMOSFET's.     

Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique

A modified floating-gate technique for measuring small gate currents in MOSFET's with very high resolution (0.01 fA) is described. Using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFET's. The conventional negative channel hot-electron gate oxide current is observed nearV_{g} = V_{d}and a small positive gate current occurs at low Vg. We argue that the dependencies of this small positive current on Vgand gate length, together with results from a separate floating-source experiment, are consistent only with hot-hole injection.     

Analysis of near-IR photon emissions from 50-nm n- and p-channel Si MOSFETs

Photon emission from n- and p-channel transistors having 50-nm effective lengths and operating in saturation were obtained by using a photon-emission microscope equipped with an HgCdTe detector. Emission spectra were acquired in the near-IR or low photon energy range (0.85-1.1 eV) and fitted to three models: Brehmsstrahlung, direct hot-hole transitions, and direct hot electron transitions. The results show that emissions in both n-channel and p-channel devices have similar Gaussian profiles, implying that the same emission mechanism is occuring in both devices. Emissions from both devices are largely due to photons generated from direct hot electron transitions within the conduction band. The mechanism is modeled as a Gaussian intensity distribution modulated by Si absorption effects since emissions were acquired through the backside.     

Hot-electron trapping in thin LPCVD SiO2dielectrics

The electron-trapping and surface-state generation characteristics of thin LPCVD SiO2dielectrics have been studied using avalanche hot-electron injection. Layered structures of thermal and LPCVD oxide have been examined as a function of anneal time and temperature. After a 1000°C anneal, bulk trapping in the LPCVD oxide was reduced to levels comparable to those in a high-quality dry thermal oxide. Sensitivity to remaining traps was reduced by the presence of a thermal oxide layer on the semiconductor surface. After a post-deposition anneal (PDA), these layered surfaces demonstrated hot-electron performance equal to that of thermal oxide within measurable limits. Also, layered structures generally demonstrated better resistance to surface-state generation than thermal oxides alone. Since less chlorine is incorporated into the layered structures during fabrication, this result is consistent with a recent model identifying broken chlorine bonds as the origin of surface states.     

Negative bias temperature instability in n-channel power VDMOSFETs

Negative gate bias is used in some applications for faster switching off the n-channel MOS devices. It is shown in this study that NBT stress-related instability in commercial n-channel power VDMOSFETs could be actually more serious than in corresponding p-channel devices. NBT stress is found to create equal V_T shifts in both device types, whereas the subsequent positive bias annealing results in more serious overall V_T instability in n-channel devices. The changes in the densities of stress-induced interface traps in two device types are equal as well, but significant amounts of NBT stress-induced border traps are only found in n-channel devices. All the results are discussed in terms of hydrogen reaction and diffusion model.     

A quantitative physical model for the band-to-bandtunneling-induced substrate hot electron injection in MOS devices

A quantitative physical model for band-to-band tunneling-induced substrate hot electron (BBISHE) injection in heavily doped n-channel MOSFETs is presented. In BBISHE injection, the injected substrate hot electrons across the gate oxide are generated by impact ionization by the energetic holes which are left behind by the tunneling electrons and become energetic when traveling across the surface high-field region in silicon. The finite available distance for the holes to gain energy for impact ionization is taken into account. A previously published theory of substrate hot electron injection is generalized to account for the spatially distributed nature of the injected electrons. This model is shown to be able to reproduce the I-V characteristics of the BBISHE injection for devices with different oxide thicknesses and substrate dopant concentration biased in inversion or deep depletion. Moreover, it is shown that the effective SiO₂ barrier height for over-the-barrier substrate hot electron injection is more accurately modeled     

Hot-hole-induced interface states build-up on deep-submicrometer LDD nMOSFETs

The hot-carrier degradation of deep-submicrometer LDD nMOSFETs under different gate-stress regimes is analysed by means of current-voltage and charge pumping characteristics. Interface state generation is found to arise as the major mechanism responsible for device degradation in the whole range of gate regimes studied.The effects of Short Electron and Hole Injection phases on hot-carrier-stressed devices are also analysed. Although SEI phases are found to be an efficient tool for revealing part of the damage generated in stresses at low gate voltages, the performance of a first SHI phase after stress at high gate bias (V_g>V_d/2) results in a significant additional degradation of the devices. This enhanced degradation is attributed to a sudden interface states build-up occurring near the Si/spacer interface only under the first hot-hole injection condition.     

A Model With Temperature-Dependent Exponent for Hot-Carrier Injection in High-Voltage nMOSFETs Involving Hot-Hole Injection and Dispersion

An improved hot-hole-involved interface-state generation model is proposed for hot-carrier injection (HCI) degradation in high-voltage (HV) nMOSFETs. This model is based on experiments over a wide range of temperatures, voltage conditions, simulation results, and the underlying physical mechanisms. The model provides a thorough picture of an HCI system in HV nMOSFETs, with hot-hole injection related to an additional maximum electric-field region. The hot-hole injection in HCI is assumed to introduce deeper localized hydrogen states in gate-oxide films than that in negative-bias temperature instabilities. This result facilitates the dispersive transport of hydrogen. Therefore, HCI degradation in HV transistors is explained within the framework of disorder-controlled hydrogen kinetics. The power-law model can successfully predict temperature dependences for HCI degradation.     

Modeling the effects of surface states on DLTS spectra of GaAsMESFETs

A resistance deep-level transient spectroscopy (DLTS) model which explains the effects of surface states on DLTS spectra of GaAs MESFETs is presented. The model includes both deep traps in the active channel under the gated region and the surface states on the ungated surface between the contacts of gate and source as well as gate and drain. Surface states are shown to result in minority holelike DLTS signals. The model reveals that the surface-state energy levels can be reliably determined from these holelike DLTS signals, although the concentrations cannot be accurately profiled due to the strong dependence of the peak magnitude of the holelike signals on the ungated surface conditions, in particular, the surface leakage current. The peak magnitude of the holelike signals are shown to depend strongly on the filling pulsewidth t_p used in a DLTS measurement. It is also shown that the peak magnitude decreases rapidly as the ratio of the gate length to the gate-source spacing is increased. It is expected that the model can be a useful tool for investigating the passivation effects of the ungated surface on a short-gate GaAs MESFET     

Fabrication of a m.o.s.f.e.t. with `spoxide? as the gate dielectric having low interface state density

Spin-on oxide (Spoxide), which forms part of the class of deposited oxides, has been found to produce a good electrical interface with silicon after HCl annealing, and surface-state densities of the order of 4 × 1010 eV?1 cm?2 are easily achievable. An n-channel depletion-type m.o.s.f.e.t. has been fabricated with Spoxide as the gate dielectric.     

Hole injection enhanced hot-carrier degradation in PMOSFETs used for systems on chip applications with 6.5–2 nm thick gate-oxides

Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (T_ox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with T_ox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.     

Evaluation of hot carrier degradation of N-channel MOSFET's with the charge pumping technique

Hot carrier degradation in n-channel MOSFET transistors has been evaluated using the charge pumping technique in addition to the conventionalI_{ds}-V_{gs}measurements. It is shown that the generation of large amounts of interface states is the primary result of moderate hot carrier stress. The simultaneous injection and recombination of injected electrons and holes is suggested to be responsible for this formation of interface states. The net charge in the oxide and interface states after any hot carrier stress is shown to be positive.     

Gate-oxide breakdown accelerated by large drain current inn-channel MOSFET's

A study of the time-dependent dielectric breakdown (TDDB) of thin gate oxides in small n-channel MOSFETs operated beyond punchthrough is discussed. Catastrophic gate-oxide breakdown is accelerated when holes generated by the large drain current are injected into the gate oxide. More specifically, the gate-oxide breakdown in a MOSFET (gate length=1.0 μm, gate width-15 μm) occurs in ~100 s at an applied gate oxide field of ~5.2 MV/cm during the high drain current stress, while it occurs in ~100 s at an applied gate oxide field of ~10.7 MV/cm during a conventional time-dependent dielectric breakdown (TDDB) test. The results indicate that the gate oxide lifetime is much shorter in MOSFETs when there is hot-hole injection than that expected using the conventional TDDB method     

Theory of emission noise from silicon field emitters

A calculation is made of the spectral density of emission fluctuations for silicon emitter tips for two emission mechanisms: emission mainly from surface states, and emission mainly from the conduction band edge. In both cases surface-state occupancy fluctuations, calculated from the generalized Nyquist formula, modulate the field emission current. The basic idea is that emission is likely to come from either surface states or from carriers in the conduction band, or both. If there are generation-recombination (G-R) fluctuations in the surface states at the emission surface, then there will be corresponding fluctuations from surface states. This G-R noise will also cause fluctuation in carrier concentrations in the emission area, and hence noise in emission from the conduction band. A discussion is given of whether the differing spectral densities for these two mechanisms may be compared with measurements to clarify which mechanism is dominant