Efficient test case generation for validation of UML activity diagrams

Unified Modeling Language (UML) is widely used as a system level specification language in embedded system design. Due to the increasing complexity of embedded systems, the analysis and validation of UML specifications is becoming a challenge. UML activity diagram is promising to modeling the overall system behavior. However, lack of techniques for automated test case generation is one major bottleneck in the UML activity diagram validation. This article presents a methodology for automatically generating test cases based on various model checking techniques. It makes three primary contributions: First, we propose coverage-driven mapping rules that can automatically translate activity diagram to formal models. Next, we present a procedure for automatic property generation according to error models. Finally, we apply various model checking based test case generation techniques to enable efficient test case generation. Our experimental results demonstrate that our approach can reduce the validation effort drastically by reducing both test case generation time and required number of test cases to achieve a functional coverage goal.     

Validation of the GSM-map protocol

This paper presents the results of experimentation performed on the application of a specification language and three conformance testing techniques to the validation of the gsm-map protocol (Global System for Mobile communication - Mobile Application Part). The gsm-map protocol is a component of the GSM radiocommunication system that describes the signaling functions required in signaling system SS7 to offer the services needed in a mobile network. The etsi standard describes this protocol in a semiformal way that we have formalized (using the sdl formal language), to improve its testability. We have then applied three different testing techniques : embedded testing techniques to perform the test of functional components embedded in the global system, global testing techniques to test the complete protocol and passive testing techniques to verify whether the protocol execution traces are accepted or not by the specification (represented by a finite state machine or by an extended finite state machine).     

New Development Method of Office Automation-Oriented PBX's

This paper describes a new methodology for developing office automation-oriented private branch exchanges (OA-PBX). Business communications are closely related to the type of business, information used in the business, and the people working in that business environment. It is expected that business communications services, man-machine interfaces, and equipment will become significantly diversified and personalized compared to conventional telephone systems offering limited services. In the development of PBX's, which are expected to play a large role in the OA environment, how to rapidly and flexibly cope with diversified and personalized business communication needs must be considered. To precisely know the user's needs and to fully reflect them in products, it is necessary to introduce a new "quick-reaction" development methodology to replace conventional ones used for systems with limited services and long life cycles. This paper proposes the rapid prototyping of OA-PBX's and associated tools. A personal computer-based PBX prototype system with circuit/packet hybrid switching functions, which is used for evaluating system functions and services, is described. A new application-oriented specification language AIFLS (architecture independent formal language for switching service specification), and an automatic programming system APROC-1, which is a kind of expert system, are used for quickly and easily making software mock-ups of switching services and man-machine interfaces and are also presented here.     

Closed-Loop Modeling in Future Automation System Engineering and Validation

This paper presents a new framework for design and validation of industrial automation systems based on systematic application of formal methods. The engineering methodology proposed in this paper is based on the component design of automated manufacturing systems from intelligent mechatronic components. Foundations of such componentspsila information infrastructure are the new IEC 61499 architecture and the automation object concept. It is illustrated in this paper how these architectures, in conjunction with other advanced technologies, such as Unified Modeling Language, Simulink, and net condition/event systems, form a framework that enables pick-and-place design, simulation, formal verification, and deployment with the support of a suite of software tools. The key feature of the framework is the inherent support of formal validation techniques achieved on account of automated transformation among different system models. The paper appeals to developers of automation systems and automation software tools via showing the pathway to improve the system development practices by combining several design and validation methodologies and technologies.     

Synthesis for real time systems: Solutions and challenges

A real time system typically combines a variety of implementation technologies and hardware architectures. Deciding how to partition the system and selecting an architectural technology for the sub-systems is by no means a trivial task. These architectural decisions, which can have a major impact on the quality and performance of the final implementation, have to be made at the early stages in the design process, when the impact of the decisions is unclear and can only be quantified using some primitive measures. p ]In this paper, we present our vision on how a next generation of design environment can aid the designer in this decision process. We first identify the problems of designing a heterogeneous real time system by walking through the design process of a complex speech recognition system. Based on this analysis, we propose a system design methodology build on top of current synthesis tools. Today, DSP synthesis tools are application and/or architecture specific, covering subparts of the application once the partitioning is made. To make them useful in the proposed methodology, a unified view on the underlying architecture assumptions is needed. Secondly, good decision making requires an “as-good-as-possible” estimation of the implications of the decision. Therefore, it is important that current manual estimation be enlarged by high level estimation and performance analysis tools. p ]The HYPERSPACE environment, which is currently under development, therefore, consists of three complementary components: a set of architecture specific compilers, a set of estimation and performance analysis tools and an architecture selection and partitioning framework, steered by the designer.     

The use of end-to-end multicast measurements for characterizinginternal network behavior

We present a novel methodology for identifying internal network performance characteristics based on end-to-end multicast measurements. The methodology, solidly grounded on statistical estimation theory, can be used to characterize the internal loss and delay behavior of a network. Measurements on the MBone have been used to validate the approach in the case of losses. Extensive simulation experiments provide further validation of the approach, not only for losses, but also for delays. We also describe our strategy for deploying the methodology on the Internet. This includes the continued development of the National Internet Measurement Infrastructure to support RTP-based end-to-end multicast measurements and the development of software tools to analyze the traces. Once complete, this combined software/hardware infrastructure will provide a service for understanding and forecasting the performance of the Internet     

HASoC—Towards a New Method for System-on-a-Chip Development

We present a novel method (HASoC) for developing embedded systems that are targeted at system-on-a-chip implementations. The object-oriented development method is based on the experiences of using our existing MOOSE technique and supports a lifecycle that explicitly separates the behavior of a system from its implementation technology. The design process, whichuses a notation based on extensions to UML-RT, begins with the incremental development and validation of an abstract executable model of a system. Subsequently, this model is partitioned into hardware and software sub-systems to create a committed model, which is mapped onto a system platform that defines the implementation environment. The methodology emphasizes the reuse of pre-existing hardware and software platforms to ease the development process. A partial example application is presented in order to illustrate the main concepts in our methodology.     

Overview of the MPEG Reconfigurable Video Coding Framework

Video coding technology in the last 20 years has evolved producing a variety of different and complex algorithms and coding standards. So far the specification of such standards, and of the algorithms that build them, has been done case by case providing monolithic textual and reference software specifications in different forms and programming languages. However, very little attention has been given to provide a specification formalism that explicitly presents common components between standards, and the incremental modifications of such monolithic standards. The MPEG Reconfigurable Video Coding (RVC) framework is a new ISO standard currently under its final stage of standardization, aiming at providing video codec specifications at the level of library components instead of monolithic algorithms. The new concept is to be able to specify a decoder of an existing standard or a completely new configuration that may better satisfy application-specific constraints by selecting standard components from a library of standard coding algorithms. The possibility of dynamic configuration and reconfiguration of codecs also requires new methodologies and new tools for describing the new bitstream syntaxes and the parsers of such new codecs. The RVC framework is based on the usage of a new actor/ dataflow oriented language called CAL for the specification of the standard library and instantiation of the RVC decoder model. This language has been specifically designed for modeling complex signal processing systems. CAL dataflow models expose the intrinsic concurrency of the algorithms by employing the notions of actor programming and dataflow. The paper gives an overview of the concepts and technologies building the standard RVC framework and the non standard tools supporting the RVC model from the instantiation and simulation of the CAL model to software and/or hardware code synthesis.     

一种HDMI-CEC控制器的设计与实现

在充分理解HDMI-CEC协议1.4版本的基础上,提出一种消费电子控制器的ASIC电路设计方案。通过对串行接口上波形进行分析,设计了两个分工不同的有限状态机来处理协议的两个重要部分:比特位时序和信息构成。利用可综合Verilog语言完成了消费电子控制器IP核的设计,并且通过NC-Verilog的仿真工具和FPGA开发板验证其功能。仿真结果表明,该设计完全符合HDMICEC通讯接口模块的要求,并且可以作为IP广泛应用于支持HDMI接口的SoC开发中去。     

A Methodology for Variable Structure System Specification: Formalism,Framework, and Its Application to ATM-Based Network System

This paper presents a formalism-based methodology and its implemented environment which constitutes a sound framework for real-time systems development. The software and/or hardware systems developed in such a formal manner are wellstructured and maintainable. We first propose a set-theoretic VSSS (Variable Structure System Specification) formalism. This formalism is the core of the presented methodology which supports a means of formal specification for real-time systems. We then develop the environment, including VSSS language definition, a translator for the language, and supporting libraries for real-time execution. Finally, a demonstration of the methodology in development of a real-time event manager, a subsystem of an ATM-based communication system, shows the correctness and efficiency of the methodology.     

Decision support and disease management: a logic engineeringapproach

This paper describes the development and application of PROforma, a unified technology for clinical decision support and disease management. Work leading to the implementation of PROforma has been carried out in a series of projects funded by European agencies over the past 13 years. The work has been based on logic engineering, a distinct design and development methodology that combines concepts from knowledge engineering, logic programming, and software engineering. Several of the projects have used the approach to demonstrate a wide range of applications in primary and specialist care and clinical research. Concurrent academic research projects have provided a sound theoretical basis for the safety-critical elements of the methodology. The principal technical results of the work are the PROforma logic language for defining clinical processes and an associated suite of software tools for delivering applications, such as decision support and disease management procedures. The language supports four standard objects (decisions, plans, actions, and enquiries), each of which has an intuitive meaning with well-understood logical semantics. The development tool set includes a powerful visual programming environment for composing applications from these standard components, for verifying consistency and completeness of the resulting specification and for delivering stand-alone or embeddable applications     

On reliable software development for microprocessors

Microprocessor software is no longer microsized. It requires the same degree of methodology as is used for developing software for large mainframes. Software development for microprocessors involves much more than just writing the machine language instructions to perform some functions. This paper describes a systematic approach for microprocessor software development based on the concepts borrowed from large systems. The suggested methodology can go a long way to promise reliable software for microprocessor based systems. The approach lays emphasis on an ordered sequence of stages, well-supported development tools, good programming practices and management backing — all integrated into a systematic method. The methodology also suggests the use of an educational plan for new staff.     

Hardware/Software Co-Design of Complex Embedded Systems: An Approach Using Efficient Process Models, Multiple Formalism Specification and Validation via Co-Simulation

This paper presents a hardware/software co-design approachwhere different specification languages can be used in parallel, allowingeffective system co-modeling. The proposed methodology introduces a processmodel that extends the traditional spiral model so as to reflect the designneeds of modern embedded systems. The methodology is supported by an advancedtoolset that allows co-modeling and co-simulation using SDL, Statecharts andMATRIX_X, and interactive hardware/software partitioning. The effectivenessof the proposed approach is exhibited through two applicati on examples: thedesign of a car window lift mechanism, and the design of a MAC layer protocolfor wireless ATM networks.     

Validation of complex vehicle systems of prototype vehicles

Complex vehicle systems (CVSs) are prototyping systems that are used to demonstrate a new functionality inside a prototype vehicle. This study focuses on an evolutionary validation process for CVSs based on a VMEbus architecture. Due to the prototype character of the system, its properties are subject to change throughout the development process. Therefore, a validation system that can be easily adapted to these changes is needed. The architecture of a feasible validation system will be described. For an exact validation of any kind of unit under test (UUT), the black-box principle should be used. To realize this kind of validation, the CVS has to be connected via its hardware interfaces to the mentioned validation system. An alternative methodology, which looks directly inside the software of the CVS, will be presented. In this case, the connection of the UUT via its hardware interfaces is avoidable. The mentioned methodology slightly affects the discovery of failures, but there is a large benefit in development time. This kind of validation shifts the test process from the road to the laboratory. The operation of such a validation system will be shown by an example.     

SpecSyn: an environment supporting the specify-explore-refineparadigm for hardware/software system design

System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the new specify-explore-refine (SER) design paradigm. This three-step approach to design includes precise specification of system functionality, rapid exploration of numerous system-level design options, and refinement of the specification into one reflecting the chosen option. A system-level design option consists of an allocation of system components, such as standard and custom processors, memories, and buses, and a partitioning of functionality among those components. After refinement, the functionality assigned to each component can then he synthesized to hardware or compiled to software. We describe the issues and approaches for each part of the SpecSyn environment. The new paradigm and environment are expected to lead to a more than ten times reduction in design time, and our experiments support this expectation     

MMV: A Metamodeling Based Microprocessor Validation Environment

With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validation challenges. The systematic validation approach starts with defining the correct behaviors of the hardware and software components and their interactions. This requires new modeling paradigms that support multiple levels of abstraction. Mutual consistency of models at adjacent levels of abstraction is crucial for manual refinement of models from the full chip level to production register transfer level, which is likely to remain the dominant design methodology of complex microprocessors in the near future. In this paper, we present microprocessor modeling and validation environment (MMV), a validation environment based on metamodeling, that can be used to create models at various abstraction levels and to generate most of the important validation collaterals, viz., simulators, checkers, coverage, and test generation tools. We illustrate the functionalities in MMV by modeling a 32-bit reduced instruction set computer processor at the system, instruction set architecture, and microarchitecture levels. We show by examples how consistency across levels is enforced during modeling and also how to generate constraints for automatic test generation.     

Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

Software Structure of No. 5 ESS--A Distributed Telephone Switching System

Most stored program controlled telephone switching systems are designed with centralized control architectures. Evolving processor technology and requirements of smooth growth over a wide size range have led system designers to take advantage of distributed processing architectures. This paper provides a conceptual framework for software partitioning on a distributed stored-program controlled switching system and discusses the resulting software structure as present in No. 5 ESS. To facilitate the software development process, a methodology based on current software engineering principles is employed. Sufficiently decoupled software components have expedited parallel development of software and provided reliability by reducing interaction and limiting propagation of errors among software components. The structuring strategy described for telephone switching is equally applicable to other distributed real-time control systems.