New TIT capacitor with ZrO2/Al2O3/ZrO2 dielectrics for 60 nm and below DRAMs

New ZrO₂/Al₂O₃/ZrO₂ (ZAZ) dielectric film was successfully developed for DRAM capacitor dielectrics of 60 nm and below technologies. ZAZ dielectric film grown by ALD has a mixture structure of crystalline phase ZrO₂ and amorphous phase Al₂O₃ in order to optimize dielectric properties. ZAZ TIT capacitor showed small Tox.eq of 8.5 Å and a low leakage current density of 0.35 fA/cell, which meet leakage current criteria of 0.5 fA/cell for mass production. ZAZ TIT capacitor showed a smaller cap leak fail bit than HAH capacitor and stable leakage current up to 550 °C anneal. TDDB (time dependent dielectric breakdown) behavior reliably satisfied the 10-year lifetime criteria within operation voltage range.     

Thermally stimulated current in SiO2

Thermally stimulated current (TSC) techniques provide information about oxide-trap charge densities and energy distributions in MOS (metal-oxide-semiconductor) capacitors exposed to ionizing radiation or high-field stress that is difficult or impossible to obtain via standard capacitance–voltage or current–voltage techniques. The precision and reproducibility of measurements through repeated irradiation/TSC cycles on a single capacitor is demonstrated with a radiation-hardened oxide, and small sample-to-sample variations are observed. A small increase in E′_δ center density may occur in some non-radiation-hardened oxides during repeated irradiation/TSC measurement cycles. The importance of choosing an appropriate bias to obtain accurate measurements of trapped charge densities and energy distributions is emphasized. A 10 nm deposited oxide with no subsequent annealing above 400°C shows a different trapped-hole energy distribution than thermally grown oxides, but a similar distribution to thermal oxides is found for deposited oxides annealed at higher temperatures. Charge neutralization during switched-bias irradiation is found to occur both because of hole-electron annihilation and increased electron trapping in the near-interfacial SiO₂. Limitations in applying TSC to oxides thinner than 5 nm are discussed.     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.     

Improved electrical properties using SrTiO3/Y2O3 bilayer dielectrics for MIM capacitor applications

In this paper, we show that the capacitance–voltage linearity of MIM structures can be enhanced using SrTiO₃ (STO)/Y₂O₃ dielectric bilayers. The C(V) linearity is significantly improved by combining two dielectric materials with opposite permittivity-voltage responses. Three STO/Y₂O₃ stacks with different thicknesses were realized and compared to a 20 nm STO single layer structure. We observed that an increase in the Y₂O₃ thickness leads to an improvement in the voltage linearity, while maintaining an overall capacitance density greater than 10 fF/μm².     

Ballistic electron emission microscopy studies of the temperature dependence of Schottky barrier height distribution in CoSi2/n-Si(1 0 0) diodes formed by solid phase reaction

Ballistic electron emission microscopy (BEEM) and ballistic electron emission spectroscopy have been performed on polycrystalline and epitaxial CoSi₂/n-Si(1 0 0) contacts at temperatures ranging from −144°C to −20°C. The ultra-thin CoSi₂ films (10 nm) were fabricated by solid state reaction of a single layer of Co (3 nm) or a multilayer of Ti (1 nm)/Co (3 nm)/amorphous-Si(1 nm)/Ti (1 nm) with a Si substrate, respectively. The spatial distribution of barrier height over the contact area obeys a Gaussian function at each temperature. The mean barrier height increases almost linearly with decreasing temperature with a coefficient of −0.23±0.02 meV/K for polycrystalline CoSi₂/Si diodes and −0.13±0.03 meV/K for epitaxial diodes. This is approximately equal to one or one-half of the temperature coefficient of the indirect energy gap in Si, respectively. It suggests that the Fermi level is pinned to different band positions of Si. The width of the Gaussian distribution is about 30–40 meV, without clear dependence on the temperature. The results obtained from conventional current–voltage and capacitance–voltage (I–V/C–V) measurements are compared to BEEM results.     

Thin-film encapsulation of top-emission organic light-emitting devices with polyurea/Al2O3 hybrid multi-layers

We developed a room-temperature encapsulation process based on multi-stack of ultra thin Al₂O₃ and polyurea layers for top-emission organic light-emitting devices (TEOLEDs). Device structure, including a capping layer for refractive-index matching and a thick polyurea buffer layer, was optimized to enhance light extraction without distorting electroluminescence spectrum. The efficiency of a TEOLED encapsulated with 5 pairs of Al₂O₃(50 nm)/polyurea(20 nm) layers was better than that of a glass-encapsulated TEOLED, whereas their color coordinates were almost identical. Moreover, the half-decay lifetime of a TEOLED encapsulated with 5 pairs of Al₂O₃/polyurea layers was 86% of that of a glass-encapsulated TEOLED. Water vapor transition rate of 5 pairs of Al₂O₃(50 nm)/polyurea(20 nm) layers on PET film was measured as low as 5 × 10⁻⁴ g/m² day.     

Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta₂O₅ films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta₂O₅ were compared. The doped Ta₂O₅ exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta₂O₅ modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.     

Thermal Ta2O5––alternative to SiO2 for storage capacitor application

Tantalum pentoxide thin layers (10–100 nm) obtained by thermal oxidation of rf sputtered Ta films on Si have been investigated with respect of their dielectric, structural and electric properties. It is established that stoichiometric Ta₂O₅ detected at the surface of the layers is reduced to tantalum suboxides in their depth. The oxide parameters are discussed in terms of a presence of an unavoidable ultrathin SiO₂ between Si and Ta₂O₅ and bond defects in both the oxide and the interface transition region. Conditions which guarantee obtaining high quality tantalum oxide with a dielectric constant of 32–35 and a leakage current less than 10⁻⁷–10⁻⁸ A/cm² at 1.5 V (SiO₂ equivalent thickness of 2.5–3 nm) are established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAMs application.     

Microstructure and electrical characteristics of Ba0.65Sr0.35TiO3 thin films etched in CF4/Ar/O2 plasma

Radio frequency magnetron sputtered Ba_0.65Sr_0.35TiO₃ (BST) thin films were etched in CF₄/Ar/O₂ plasma by magnetically enhanced reactive ion etching technique. The etching characteristics of BST films were characterized in terms of microstructure and electrical properties. Atomic force microscopy and X-ray diffraction results indicate that the microstructure of the etched BST film is degraded because of the rugged surface and lowered intensities of BST (1 0 0), (1 1 0), (1 1 1) and (2 0 0) peaks compared to the unetched counterparts. Dielectric constant and dielectric dissipation of the unetched, etched and postannealed-after-etched BST film capacitors are 419, 346, 371, 0.018, 0.039 and 0.031 at 100 kHz, respectively. The corresponding dielectric tunability, figure of merit and remnant polarization are 19.57%, 11.56%, 17.25%, 10.87, 2.96, 5.56, 3.62 μC/cm², 2.32 and 2.81 μC/cm² at 25 V, respectively. The leakage current density of 1.75 × 10⁻⁴ A/cm² at 15 V for the etched BST capacitor is over two orders of magnitude higher than 1.28 × 10⁻⁶ A/cm² for the unetched capacitor, while leakage current density of the postannealed-after-etched capacitor decreases slightly. It means that the electrical properties of the etched BST film are deteriorated due to the CF₄/Ar/O₂ plasma-induced damage. Furthermore, the damage is alleviated, and the degraded microstructure and electrical properties are partially recovered after the etched BST film is postannealed at 923 K for 20 min under a flowing O₂ ambience.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Pentacene thin-film transistors with sol-gel derived amorphous Ba0.6Sr0.4TiO3 gate dielectric

An amorphous Ba_0.6Sr_0.4TiO₃ (BST) film with the thickness of 200 nm was deposited on indium-tin-oxide (ITO)-coated glass substrate through sol-gel route and post-annealing at 500 °C. The dielectric constant of the BST film was determined to be 20.6 at 100 kHz by measuring the Ag/BST/ITO parallel plate capacitor, and no dielectric tunability was observed with the bias voltage varying from −5 to 5 V. The BST film shows a dense and uniform microstructure as well as a smooth surface with the root-mean-square (RMS) roughness of about 1.4 nm. The leakage current density was found to be 3.5 × 10⁻⁸ A/cm² at an applied voltage of −5 V. The transmittance of the BST/ITO/glass structure is more than 70% in the visible region. Pentacene based transistor using the as-prepared BST film as gate insulator exhibits a low threshold voltage of −1.3 V, the saturation field-effect mobility of 0.68 cm²/Vs, and the current on/off ratio of 3.6 × 10⁵. The results indicate that the sol-gel derived BST film is a promising high-k gate dielectric for large-area transparent organic transistor arrays on glass substrate.     

Walk-out phenomena in 6H-SiC mesa diodes with SiO2/Si3N4 passivation and charge trapping in dry and wet oxides on N-type 6H-SiC

The drift or “walk-out” of the breakdown voltage in 6H-SiC mesa diodes passivated by a double layer of 1000 Å SiO₂ and 3000 Å Si₃N₄ was studied and related to the charge trapping in the oxide. The first-order trapping kinetics using four distinct electron traps with trapping cross-sections in the range 10⁻¹⁶ to 10⁻¹⁹ cm² were found to best describe the breakdown voltage drift curves. The wet oxide trapping cross-sections are 2 to 10 times larger compared to the dry oxide ones, resulting in about one order of magnitude faster charging of the traps. No significant differences in the amount of drift and saturation level of breakdown voltage were found between the different passivations. The influence of UV illumination, supplied by a HeCd laser with wavelength 325 nm, on the walk-out characteristics and on the reverse current was also investigated. The build-up of the surface states was observed in wet oxide under UV illumination and DC stress. The results are consistent with the coexistence of large concentrations of positive charge and acceptor type deep interface electron traps. The walk-out is a result of the acceptor states being filled by hot electrons supplied by the mechanism of avalanche injection. The suitability of the walk-out measurements as a tool for characterisation of the charge trapping properties of the passivation is demonstrated.     

A study on the improved programming characteristics of flash memory with Si3N4/SiO2 stacked tunneling dielectric

The programming characteristics of memories with different tunneling-layer structures (Si₃N₄, SiO₂ and Si₃N₄/SiO₂ stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO₂/Si₃N₄ stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO₂ or Si₃N₄ for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO₂/Si₃N₄ stacked tunneling layer at V_cg = 10 V and V_ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10¹⁶–2 × 10¹⁷ cm⁻³, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current.     

Optical and electrical characterization of the electron beam gun evaporated TiO2 film

We report measured evolutions of the optical band gap, refractive index and relative dielectric constant of TiO₂ films obtained by electron beam gun evaporation and annealed in an oxygen environment. A negative shift of the flat band voltage with increasing annealing temperatures, for any film thickness, is observed. A dramatic reduction of the leakage current by about four orders of magnitude to 5×10⁻⁶ A cm⁻² (at 1 MV cm⁻¹) after 700°C and 60 min annealing is found for films thinner than 15 nm. The basic carrier transport mechanisms at different ranges of applied voltage such as hopping, space charge limited current and Fowler–Nordheim is established. An equivalent SiO₂ thickness in order of 3.5 nm is demonstrated.     

High temperature transport kinetics in heteroepitaxial LaFeO3 thin films

Heteroepitaxial LaFeO₃(1 1 0) thin films with a thickness of 150 nm were grown on LaAlO₃(0 0 1) by reactive sputtering in an inverted cylindrical magnetron geometry. Equilibrium conductivity was measured as a function of partial pressure of oxygen at T=1000 °C, and logσ plotted vs. logP(O₂) showed a minimum in conductivity for P(O₂)=10⁻¹¹ atm and a linear response between 10⁻¹⁰ and 1 atm. This linear response makes thin films of LaFeO₃ a promising material for oxygen sensor applications. We have also measured the time response of the film conductivity upon an abrupt change in the partial pressure of ambient oxygen from 10⁻² to 10⁻³ atm, which was determined at 60 s for T=700 °C and <3.5 s at T=1000 °C.     

Degradation kinetics of ultrathin HfO2 layers on Si(1 0 0) during vacuum annealing monitored with in situ XPS/LEIS and ex situ AFM

The evolution of HfO₂(3–5 nm)/SiO₂(0.5 nm)/Si(1 0 0) stacks during vacuum annealing was monitored in situ with the combination of X-ray photoelectron spectroscopy and low energy ion scattering techniques and supplemented with atomic force microscopy analysis to investigate the mechanism that triggers HfO₂ degradation with Hf silicide formation. The reduction of SiO₂ interfacial layer and the formation of local paths for SiO escape into vacuum are believed to be critical at vacuum annealing above T > 850 °C for the reaction between HfO₂ and Si to start and eventually lead to the degradation of the former.     

The structural and electrical properties of the SrTa2O6/In0.53Ga0.47As/InP system

The structural and electrical properties of SrTa₂O₆(SrTaO)/n-In_0.53GaAs_0.47(InGaAs)/InP structures where the SrTaO was grown by atomic vapor deposition, were investigated. Transmission electron microscopy revealed a uniform, amorphous SrTaO film having an atomically flat interface with the InGaAs substrate with a SrTaO film thickness of 11.2 nm. The amorphous SrTaO films (11.2 nm) exhibit a dielectric constant of ∼20, and a breakdown field of >8 MV/cm. A capacitance equivalent thickness of ∼1 nm is obtained for a SrTaO thickness of 3.4 nm, demonstrating the scaling potential of the SrTaO/InGaAs MOS system. Thinner SrTaO films (3.4 nm) exhibited increased non-uniformity in thickness. From the capacitance-voltage response of the SrTaO (3.4 nm)/n-InGaAs/InP structure, prior to any post deposition annealing, a peak interface state density of ∼2.3 × 10¹³ cm⁻² eV⁻¹ is obtained located at ∼0.28 eV (±0.05 eV) above the valence band energy (E_v) and the integrated interface state density in range E_v + 0.2 to E_v + 0.7 eV is 6.8 × 10¹² cm⁻². The peak energy position (0.28 ± 0.05 eV) and the energy distribution of the interface states are similar to other high-k layers on InGaAs, such as Al₂O₃ and LaAlO₃, providing further evidence that the interface defects in the high-k/InGaAs system are intrinsic defects related to the InGaAs surface.     

Plasma-enhanced flexible metal-insulator-metal capacitor using high-k ZrO2 film as gate dielectric with improved reliability

We demonstrate a new flexible metal-insulator-metal capacitor using 9.5-nm-thick ZrO₂ film on a plastic polyimide substrate based on a simple and low-cost sol-gel precursor spin-coating process. The surface morphology of the ZrO₂ film was investigated using scan electron microscope and atomic force microscope. The as-deposited ZrO₂ film under suitable treatment of oxygen (O₂) plasma and then subsequent annealing at 250 °C exhibits superior low leakage current density of 9.0 × 10⁻⁹ A/cm² at applied voltage of 5 V and maximum capacitance density of 13.3 fF/μm² at 1 MHz. The as-deposited sol-gel film was completely oxidized when we employed O₂ plasma at relatively low temperature and power (30 W), hence enhancing the electrical performance of the capacitor. The shift (Zr 3d from 184.1 eV to 184.64 eV) in X-ray photoelectron spectroscopy of the binding energy of the electrons towards higher binding energy; clearly indicates that the O₂ plasma reaction was most effective process for the complete oxidation of the sol-gel precursor at relatively low processing temperature.     

Templates for LaAlO3 epitaxy on silicon

As direct epitaxy of crystalline LaAlO₃ on silicon has not been realized yet, we investigated the use of a template between the high-κ and the substrate. We performed calculations in the Density Functional Theory framework for two possible templates: a Sr_0.5O monolayer and a 0.5 nm thick γ-Al₂O₃(0 0 1) layer. We firstly found that in the Sr_0.5O monolayer case, care must be taken for the LaAlO₃ starting sequence in order to expect good band offsets with silicon. In the γ-Al₂O₃ case, a more complex engineering of the interface is needed. Nonetheless, we found stable interfaces and a surface reconstruction in agreement with experimental observations. Moreover, these interfaces exhibit insulating properties and insight calculations for a Si–γ-Al₂O₃–LaAlO₃ superstructure lead us to a 1.9 eV conduction band offset.     

Time-dependent dielectric breakdown of SiO2 films in a wide electric field range

We have performed time dependent dielectric breakdown measurement of SiO₂ films in the electric field (E_OX) range 7–13.5 MV/cm and evaluated the electric field dependence of intrinsic lifetime, using both area and temperature dependences of oxide lifetime. We have evaluated the electric field dependence of time to breakdown (t_BD) below 125°C, because the activation energy of intrinsic lifetime changes at 125°C t_BD of 7.1 and 9.6 nm oxides is not proportional to exp(E_OX) but proportional to exp(1/E_OX). This suggests that the breakdown mechanism of 9.6 and 7.1 nm oxides is the same and adheres to the anode hole injection model. However, the breakdown mechanism of 4.0 nm oxides is not the same as that of 7.1 and 9.6 nm oxides. The slope of log(t_BD) versus 1/E_OX plot in 4.0 nm oxide increases with decreasing oxide fields. The intrinsic lifetime in the positive gate bias decreases with increasing oxide thicknesses in the range of electric fields employed in the present experiment.