双优先级的信道成组ATM交换性能分析

分析了既有丢失优先级又有服务优先级的信道成组ＡＴＭ交换系统的性能。在ＡＴＭ交换中，各种业务分别有不同的服务质量要求。提出了用部分缓冲共享方案给予丢失率要求高的业务以较多缓冲空间，同时引入高，低优先级队列，使进时延的业务先得到服务。研究了缓冲阈值，业务量及信道成组技术对系统性能的影响。模拟结果与理论分析吻合。     

雷达组网通信中的ATM交换机

介绍了ＡＴＭ交换技术在雷达组网通信中的应用。通过对基于中央处理站的雷达组网通信技术需求的分析，提出了一种类似于用户—服务器模式的ＡＴＭ交换结构。ＡＴＭ技术是Ｂ—ＩＳＤＮ的基础，ＡＴＭ交换技术是ＡＴＭ技术的核心，它不仅可用于民用通信业务，而且对于电子干扰环境下雷达网对密集多目标跟踪时所涉及的通信业务也很有效。文章对ＡＴＭ交换机在雷达网中的数据交换作了分析，并以计算机仿真手段评估了三种特定通信环境下输出缓冲型ＡＴＭ交换机的利用率和输出队列概率分布情况。     

ABR业务流量控制中的是速率反馈

ＡＢＲ（Ａｖａｉｌａｂｌｅ Ｂｉｔ Ｒａｔｅ）业务可以提高ＡＴＭ网络的利用率，能让用户ＬＡＮ通过广域网进行高吞吐量、低丢失率的互通。可以预计，未来ＡＴＭ网上的数据业务将主要用ＡＢＲ连接来传输。ＡＢＲ业务中的首要问题是流量控制。文章在比较了几种流量控制方案后，认为显速率反馈是ＡＢＲ业务流及拥塞控制的一个有效方法，是完善ＡＢＲ业务的一个重要手段，并对显速率算法作了进一步研究。     

有线电视网络升级和业务开发

本文结合青岛有线电视网建设和发展中遇到的实际问题谈了有线广播电视网应建成一个什么样的网，如何升级改造和如何开展多功能业务的一些思路。重点介绍了青岛市区建高１５５０ｎｍ干线网的技术方案，市区ＡＴＭ骨干网技术方案，高速数据广播和ＮＶＯＤ技术方案，还介绍了利用ＡＴＭ骨干网开展Ｉｎｔｅｒｎｅｔ业务，计算机联网和利用ＡＴＭ网与ＨＦＣ网相结合开展ＶＯＤ业务的技术方案。     

异步转移模式（ATM）的研究现状与前景

ＡＴＭ是实现宽带综合业务数字网（Ｂ－ＩＳＤＮ）关键技术之一。本文综述了ＡＴＭ近几年来在网路控制、业务模型、资源分配、允许接入控制、流量控制以及选路控制等诸多方面的研究进展与存在问题，并提出了实现ＡＴＭ综合多种业务与有效利用网路资源这一目标的途径。     

宽带综合业务局域网中ATM队列管理结构的研究

本文通过对基于ＡＴＭ（异步传输方式）中的一种管理算法－虚时钟算法的几种队列管理实现方法的比较，提出了在ＢＬＳＬＮ（宽带综合业务局域网）中的虚时钟算法，同时设计了一种易实现的ＢＬＳＬＮ队列管理方法，完成了ＢＬＳＬＮ的模型设计与实现。     

基于ATM的宽带业务网

本文着重讨论了实现ＡＴＭ的关键技术和ＡＴＭ实现业务综合的机理，以及Ｉｎｔｅｒｎｅｔ的火爆使ＡＴＭ走向商用的原因和ＡＴＭ作为实现Ｂ－ＩＳＤＮ一个有效方案的理由。     

一项运用帧中继标准的新举措

一项运用帧中继标准的新举措１９９５年８月，帧中继论坛制定了几项标准并通过了一项实施规范（ＩＡ），允许帧中继（ＦＲ）与ＡＴＭ业务间无缝连接。这项由ＦＲ和ＡＴＭ论坛联手开发的ＦＲ至ＡＴＭ永久虚连接业务联网的执行方案，使ＦＲ与ＡＴＭ终端设备无须配备任何专门...     

国外ATM业务及资费分析

本文介绍了国际ＡＴＭ业务的发展状况，分析了国外ＡＴＭ业务的资费情况，对美国一些公司的ＡＴＭ业务的资费水平进行了比较，并探讨了ＡＴＭ业务资费结构和资费水平，供我国有关文献参考借鉴。     

ATM网中标准UPC算法及其实现

本文介绍了ＡＴＭ网络中用户参数控制的策略，着重讨论了两种标准的峰值信元速率控制算法，提出了可能的电路实现方案，并分析了用户参数控制策略与业务性能的关系。     

Performance study of an input and output queueing ATM switch with a window scheme and a speed constraint

In this paper, we study the performance of an input and output queueing switch with a window scheme and a speed constraint. The performance of a non-blocking ATM switch can usually be improved by increasing the switching speed. Also, the performance of a switch can be improved using a window scheme by relaxing the first-in-firstout (FIFO) queueing discipline in the input queue. Thus, one can expect that a combined scheme of windowing and a speed constraint can improve further the performance of the packet switch. Here, we analyze the maximum throughput of the input and output queueing switch with a speed constraint combined with windowing, and show that it is possible to obtain high throughput with a small increment of speed-up and window size. For analysis, we model the HOL queueing system as a virtual queueing system. By analyzing the dynamics of HOL packets in this virtual queueing model, we obtain the service probability of the HOL server as a function of output contention capabilities. Using the result, we apply the flow conservation relation to this model and obtain the maximum throughput. The analytical results are verified by simulation.     

A discrete-time queueing model of the shared buffer ATM switch with bursty arrivals

We model the shared buffer ATM switch as a discrete-time queueing system. The arrival process to each port of the ATM switch is assumed to be bursty and it is modelled by an interrupted Bernoulli process. The discrete-time queueing system is analyzed approximately. It is first decomposed into subsystems, and then each subsystem is analyzed separately. The results from the subsystems are combined together through an iterative scheme. The analysis of each subsystem involves the construction of the superposition of all the arrival processes to the switch. Comparisons with simulation data showed that the approximate results have a good accuracy.Supported in part by DARPA under Grant No. DAEA18-90-C-0039.Work done while on a sabbatical leave of absence at the Computer Science Department of North Carolina State University.     

Design of a generalized priority queue manager for ATM switches

Meeting quality of service (QoS) requirements for various services in ATM networks has been very challenging to network designers. Various control techniques at either the call or cell level have been proposed. In this paper, we deal with cell transmission scheduling and discarding at the output buffers of an ATM switch. We propose a generalized priority queue manager (GPQM) that uses per-virtual-connection queueing to support multiple QoS requirements and achieve fairness in both cell transmission and discarding. It achieves the ultimate goal of guaranteeing the QoS requirement for each connection. The GPQM adopts the earliest due date (EDD) and self-clocked fair queueing (SCFQ) schemes for scheduling cell transmission and a new self-calibrating pushout (SCP) scheme for discarding cells. The GPQM's performance in cell loss rate and delay is presented. An implementation architecture for the GPQM is also proposed, which is facilitated by a new VLSI chip called the priority content-addressable memory (PCAM) chip     

Priority queueing strategies and buffer allocation protocols fortraffic control at an ATM integrated broadband switching system

The problem of furnishing an asynchronous transfer mode (ATM) based broadband-ISDN (B-ISDN) with two bearer services supporting different grades of transfer quality is addressed. The focus is on priority bandwidth and buffer management in the ATM communications nodes (switches, multiplexers or concentrators, and expanders) in the context of a multichannel network architecture. Detailed queueing analyses and simulations and results are provided to evaluate the differentiation between traffic classes that can be achieved by different strategies. The implementation complexity of the different schemes is discussed. Various priority queueing strategies characterized mainly by different degrees of resource sharing and a general system model for performance evaluation are introduced. Performance comparisons and design tradeoffs are addressed     

AN ATM-LIKE SYSTEM ARCHITECTURE FOR SATELLITE COMMUNICATIONS INCLUDING ON-BOARD SWITCHING

In this paper, an ATM system architecture for satellite communications is described. The proposed architecture includes an on-board switch and implements the adaptation of real-time services (e.g. voice and video) and non-real-time services (e.g. data) to the satellite communication link, while achieving statistical advantage. To this end, the ATM traffic categories defined in recent specifications^1,2 are utilized. Real-time and non-real-time traffic components are simultaneously supported by a TDMA/TDM on the satellite uplink/downlink, respectively. By exploiting the burstiness of real-time traffic, the proposed satellite system architecture achieves a significant increase of the overall system throughput. After describing the satellite system architecture and addressing scheme, we derive analytical models, by using sophisticated queueing models that allow a very accurate performance evaluation and an easy dimensioning of the data buffers. The proposed model is validated with simulations. The main result is the assessed feasibility of on-board buffers with current technology, even under very strict performance requirements on cell loss ratio and for quite high load values (e.g. 80 per cent of the downlink capacity). Finally, a congestion control scheme, based on a combination of preventive and reactive strategies, is proposed and analysed.     

Network delay analysis of a class of fair queueing algorithms

A self-clocked fair queueing (SCFQ) scheme has been proposed by Golestani (see Proc. IEEE INFOCOM, p. 636-636, 1994) as an easily implementable version of fair queueing. In this paper, the worst case network delay performance of a class of fair queueing algorithms, including the SCFQ scheme, is studied. We build upon and generalize the methodology developed by Parekh and Gallager (see ACM/IEEE Trans. Networking, vol.1, no.3, p.344-357, 1993, and vol.2, no.2, p.137-150, 1994) to study this class of algorithms based on the leaky-bucket characterization of traffic. Under modest resource allocation conditions, the end-to-end session delays and backlogs corresponding to this class of algorithms are shown to be bounded. For the SCFQ scheme, these bounds are larger, but practically as good as the corresponding bounds for the PGPS scheme. It is shown that the SCFQ scheme can provide adequate performance guarantees for the delay-sensitive traffic in ATM     

Design and performance of Multinet switch: a multistage ATM switcharchitecture with partially shared buffers

A new ATM switch architecture is presented. Our proposed Multinet switch is a self-routing multistage switch with partially shared internal buffers capable of achieving 100% throughput under uniform traffic. Although it provides incoming ATM cells with multiple paths, the cell sequence is maintained throughout the switch fabric thus eliminating the out-of-order cell sequence problem. Cells contending for the same output addresses are buffered internally according to a partially shared queueing discipline. In a partially shared queueing scheme, buffers are partially shared to accommodate bursty traffic and to limit the performance degradation that may occur in a completely shared system where a small number of calls may hog the entire buffer space unfairly. Although the hardware complexity in terms of number of crosspoints is similar to that of input queueing switches, the Multinet switch has throughput and delay performance similar to output queueing switches     

An IP transport and routing architecture for next-generationsatellite networks

Over the past several years, a number of new satellite systems have been proposed to provide high-speed Internet and multimedia services to businesses and home users. These proposals have been driven by the desire of network operators to reach end users that do not have cost effective access to other alternatives such as fiber, DSL, and cable, and by the availability of new spectrum (Ka-band) for use by new satellite services. The proposed systems generally employ multiple high-power spot beams, an onboard fast packet switch, and a demand-assigned multiple access scheme to provision IP-based services. In this article we concentrate on a geosynchronous satellite system where packet transport and switching within the satellite system are based on ATM. We describe an IP/ATM interworking and IP routing architecture that is driven by three main requirements: (1) the ability to support ATM SVCs between hundreds of thousands of satellite terminals by a single ATM switch located onboard; (2) a scalable IP routing architecture that does not result in large volumes of routing traffic to be transported over the satellite; and (3) the ability to segment the satellite terminals for routing and administrative control by ISPs and enterprise networks     

Modelling ARQ for a High-Speed ATM-Based Wireless LAN

An Automatic Repeat Request (ARQ) scheme is proposed for a wireless ATM LAN based on the MEDIAN concept. Simulations have been performed to demonstrate the consequences of ARQ inclusion in terms of required buffer capacity and resulting cell end-to-end delay. In particular, the behaviour of the ARQ-enhanced system for real-time traffic under non error-free conditions has been examined. The main result of the simulations is that, due to specific properties of the MEDIAN wireless ATM LAN, the proposed ARQ scheme is suitable for real-time ATM services, while yielding virtually error-free links. Next to low cell delay, it features low overhead and low processing complexity whereas it can be readily combined with a simple and efficient MAC scheme.     

ATM交换中输入输出开窗排队算法的改进

本文为ＡＴＭ交换系统提出了一种改进的输入输出开窗算法，通过在原有输入开窗排队算法中引入因子Ｐｓ，改进算法允许至多Ｐｓ个信元同时到达同一输出口，并利用输入输出缓冲队列来减缓输出碰撞，改进的开窗算法不仅能得到几科与输出排队一亲的最优吞吐和延迟性能，还具有好得多的分组单元丢失性能，尤其适合缓冲容量有限的情形，因而不失为一有效的ＡＴＭ交换系统设计方案，本文讨论了算法及其复杂度分析，给出了计算机仿真的性能结