A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy

A six-mask 1-µm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p⁺substrate and a retrograde n-well. Self-aligned TiSi2is formed on n⁺and p⁺diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n⁺poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is demonstrated that this CMOS technology is latchup free since the holding voltage for latchup is higher than 5 V.     

Selective epitaxial growth for the fabrication of CMOS integrated circuits

A process is described for the fabrication of CMOS integrated circuits which combines the epitaxial lateral overgrowth (ELO) technique with the concept of selective epitaxy. The resulting epitaxial material is shown to have a low defect density. Transistors fabricated in the selective epitaxy are shown to have characteristics which are a function of the epitaxial deposition conditions, the substrate orientation and dopant concentration, and the epitaxial layer thickness. Minimum device leakage currents were 250 pA/µm of channel width for n-channel devices fabricated in a p-well and 1.0 pA/µm for devices fabricated on p-substrates. The higher leakage currents for devices fabricated in a well are believed to be a result of the narrow vertical spacing (0.3-0.5 µm) between the n⁺source-drain regions and the n⁺substrate.     

Laser recrystallized polysilicon for high performance I2L

A key process innovation that has the potential to make very significant improvements in the performance of (integrated injection logic) I²L is proposed and demonstrated. The process is based on replacing the p⁺extrinsic base-n^-substrate parasitic diode with an oxide capacitor, This would eliminate injection current losses to the underlying substrate, thus improving the current gain, the minimum propagation delay time, and the speed-power product of the structure. A buried oxide I²L structure of this type may be realized via the use of pulsed or CW laser recrystallization of polysilicon. An interesting feature of the proposed method is that the crystal material over SiO2would not be used for the active transistor area, thus relaxing the stringent material requirements of bipolar devices. The polysilicon may be deposited on a p⁺base patterned thermal oxide by LPCVD or by deposition in a high temperature epitaxial reactor. The realization of such structures is demonstrated here specifically for the case of pulsed laser annealing of polysilicon deposited by either of the above mentioned ways.     

Vertical current components in integrated injection logic

Analytic expressions representing a double diffused transistor impurity profile are used to calculate the current components in IIL structures. The expression for the hole current is given for IIL structures with the epitaxial layer grown on a wide n⁺substrate and for buried layer structures. It was found that an equivalent recombination velocity at the n-n⁺interface,S_{nn+}, is of order 10²higher in buried layer structures than in structures with the epitaxial layer grown on a wide n⁺substrate for comparable doping levels. Results obtained using the analytic expressions are compared with those obtained using a computer program which includes heavy doping effects and doping level mobility dependence. Both calculated and computed results are also compared with measured currents for a given IIL structure with the epitaxial layer grown on a wide n⁺substrate. The calculated and the computed results are in good agreement with the experimental results.     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

A new cobalt salicide technology for 0.15-μm CMOS devices

A new cobalt (Co) salicide technology for sub-quarter micron CMOS transistors has been developed using high-temperature sputtering and in situ vacuum annealing. Sheet resistance of 11 Ω/□ for both gate electrode and diffusion layer was obtained with 5-nm-thick Co film. No line width dependence of sheet resistance was observed down to 0.15-μm-wide gate electrode and 0.33-μm-wide diffusion layer. The high temperature sputtering process led to the growth of epitaxial CoSi ₂ layers with high thermal stability. By using this technology 0.15 μm CMOS devices which have shallow junctions were successfully fabricated     

Characteristics of a new isolated p-well structure using thinepitaxy over the buried layer and trench isolation

An isolated p-well structure for deep-submicrometer BiCMOS LSIs is proposed. The structure consists of a retrograde p-well in an n-type thin epitaxial layer over an n⁺ buried layer, and trench isolation. Latchup characteristics in this CMOS structure and breakdown characteristics of the shallow p-well are studied on test devices. Excellent latchup immunity and sufficient voltage tolerance are obtained with a thin 1-μm epitaxial layer. A CMOS 1/8 dynamic-type frequency divider using this well structure functions properly up to 3.2 GHz at a 2-V supply voltage     

Use of the polysilicon gate layer for local interconnect in a CMOStechnology incorporating LDD structures

In conventional single-level polysilicon technologies, the polysilicon gate layer can be used as an interconnect layer through buried contacts between polysilicon and one type of junction (usually n ⁺) in the underlying substrate. The formation and characteristics of buried contacts between n⁺ and p⁺ junctions and a single polysilicon gate layer are discussed. In addition, it is shown that the obstacles posed by the inclusion of oxide-sidewall spacers (common in present-day VLSI CMOS technologies) are surmountable with respect to the formation of useful buried contacts and the resultant local interconnect level that they provide     

A self-aligned retrograde twin-well structure with buried p+-layer

A self-aligned retrograde twin-well structure with a buried p⁺-layer surrounding the n-well is presented. The retrograde twin well and buried p⁺-layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions, and the channel stop processes are eliminated by using tight spatial distributions of retrograde n- and p-wells. This simple process is compatible with both local oxidation of silicon (LOCOS) and trench isolation processes and allows a scalable CMOS structure for very tight n⁺-to-p⁺ spacing. The present CMOS structure provides high latchup immunity at 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stop dopings     

20-GHz high-power GaAs DDR-IMPATT diodes with a p+-p-n-n+structure

GaAs DDR (double-drift-region)-IMPATT diodes have been made by using epitaxial wafers with a p⁺-p-n-n⁺structure, which was made by successive liquid-phase epitaxy of p⁺, p, and n layers on n⁺substrate in one heat cycle. On the diodes with copper heat sink, the maximum CW output power of 1.2 W was obtained at 21 GHz with the efficiency of 15.6 percent.     

A self-aligned retrograde twin-well structure with buried p+-layer

The retrograde twin wells and buried p⁺ layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions. This simple process allows a scalable CMOS structure for the very tight n⁺-to-p⁺ spacing. It provides latch-up immunity at the 1.5-μm n⁺-to-p⁺ spacing and good isolation characteristics without additional n- and p-channel stops     

Low-resistance self-aligned Ti-silicide technology for sub-quartermicron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi₂ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi₂ films were achieved on all narrow, long n⁺ and p⁺ poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi₂ films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n⁺ and p⁺ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi₂ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi₂ films     

A new and improved borderless contact (BLC) structure forhigh-performance Ti-salicide in sub-quarter micron CMOS devices

We demonstrate a new and improved borderless contact (BLC) Ti-salicide process for the fabrication of sub-quarter micron CMOS devices. A low-temperature chemical vapor deposition (CVD) SiO_x N_y film to act as the selective etching stop layer and the additional n⁺ and p⁺ source-drain double implant structure (DIS) are employed in the studied device. The additional n⁺ and p⁺ DIS can reduce the junction leakage current, which is usually enhanced by BLC etching near the edge of shallow trench isolation (STI). The process window is enlarged. Furthermore, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration     

0.1-μm p+-GaAs gate HJFET's fabricated using two-stepdry-etching and selective MOMBE growth techniques

This paper reports the first successful fabrication of high-performance, 0.1-μm p⁺-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-μm or less gate-openings with a high aspect-ratio of 3.5 in SiO ₂ film are achieved. In addition, by using the gate electrode filling technique with selective MOMBE p⁺-GaAs growth, 0.1-μm voidless p⁺-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Ce^ext _f) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-μm, T-shaped, p⁺-gate n-Al_0.2Ga_0.8As/In_0.25Ga_0.75 As HJFET exhibits a high gate turn-on voltage (V_f) of about 0.9 V, and a good gm_max of 435 mS/mm. Also, an excellent microwave performance of f_T=121 GHz and f_max =144 GHz is achieved due to the C^ext_f reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's     

A low-voltage high-speed silicon photodiode with buried isolation region for short-haul optical-fiber communications

A new epitaxial silicon p-i-n photodiode has been developed for short-haul optical-fiber communications that can be operated at biases as low as 4 V. The device has a heavily doped 5-µm-thick p⁺⁺isolation-region between the p⁺substrate and the π-epitaxial layer. Fast rise and fall times (2 ns), and low leakage current (40 pA) result from the recombination and trapping of the minority-carrier electrons in the substrate. Experimental results on such an n⁺-π-p⁺⁺-p⁺device with 1.1-mm²photosensitive area and 25-µm epi-layer thickness show quantum efficiency of 80 percent at 825-nm wavelength.     

A comprehensive study of suppression of boron penetration byamorphous-Si gate in P+-gate PMOS devices

This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p⁺-gate devices. The characteristics and reliability for different gate structures (poly-Si, α-Si, poly-Si/poly-Si, poly-Si/α-Si, α-Si/poly-Si, and α-Si/α-Si) in p ⁺ polygate PMOS devices are investigated in detail. The suppression of boron penetration by the nitrided gate oxide is also discussed. The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p⁺ polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate. Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance. The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p⁺-gate PMOS device for future dual-gate CMOS process. In addition, by employing a long time annealing at 600°C prior to p⁺-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate. Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect     

Surface induced latchup in VLSI CMOS circuits

Experimental as well as theoretical results on the latch-up effect in CMOS structures with and without an epitaxial layer are presented. In structures with an epitaxial layer the critical current for latchup firing is two orders of magnitude higher and latchup is essentially surface controlled. The strong surface effect observed is a consequence of the gate influence of surface conduction of the field oxide MOSFET's and on current gains of the bipolar transistors. Latch-up sensitivity can be decreased by increasing p⁺/p-well and n⁺/n-well spacing, by decreasing expitaxial layer thickness and by increasing substrate doping. In reducing the lateral dimensions, short-channel effects of the field oxide transistors imply the most severe limitations for latch-up immunity.     

Device isolation in high-density LOCOS-isolated CMOS

Leakage paths between n- and p-channel devices in high packing density CMOS circuits fabricated using standard LOCOS isolation are investigated. Experimental results and the results of two-dimensional numerical modeling are presented for both a conventional n-well and a retrograde n-well technology. Adequate isolation for 5-V circuit operation is demonstrated for retrograde n-well structures with a 1.8-µm n⁺to p⁺diffusion separation, and for conventional n-well structures with a 2.4-µm n⁺to p⁺diffusion separation. In both cases, good latchup protection is also demonstrated using thin p^-on p⁺epitaxial material.     

Sub-1/4-μm dual-gate CMOS technology using in-situ dopedpolysilicon for nMOS and pMOS gates

A new dual poly-Si gate CMOS fabrication process is proposed. The incorporated technology features a boron-penetration-resistant MBN gate structure for pMOSFET's, and a dual poly-Si gate CMOS process involving separate depositions of in-situ doped n⁺ and p⁺ poly-Si for the nMOS and pMOS gates, 0.2-μm CMOS devices with 3.5-nm gate oxide have been successfully fabricated. The advantages of the new process are demonstrated on these test devices. A CMOS 1/16 dynamic frequency divider fabricated by the new process functions properly up to 5.78 GHz at a 2-V supply voltage     

The formation of shallow low-resistance source—Drain regions for VLSI CMOS technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-µm transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p⁺regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n⁺and p⁺junction depths are 0.22 µm and of 8 Ω/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.