Comparative redundancy, an alternative to triple modular redundant system design

A new scheme for implementing highly reliable digital systems is proposed. The method has a circuitry overhead which is comparable to that of the triple modular redundancy (TMR) scheme, although it is shown to have a reliability, and more importantly a mean time to failure, improvement well beyond that expected from the standard TMR systems. The reliability and mean time to failure are both developed from a discrete state, continuous time, Markov model of the new system. The results for the reliability and mean time to failure characteristics for this new design of system, termed comparative redundancy, are compared to both TMR and a single unit.     

Microcomputer reliability improvement using triple-modular redundancy

Triple-modular redundancy (TMR) is a classical technique for improving the reliability of digital systems. However, applying TMR to microcomputer systems may not improve overall system reliability because voter circuits may contribute as much to system unreliability as the microprocessors themselves. We examine the issues that affect the effectiveness of TMR for transient recovery and the reliability of semiconductor memory systems. With careful application, TMR can improve the mission time of a small system by a factor of 3 or more.     

Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits

Hardware Trojans are malicious alterations in Integrated Circuits (ICs) that leak confidential information or disable the entire IC. The detection of these Trojans is performed through logic or side channel based testing. Under sub-nm technologies the detection of Hardware Trojans will face more problems due to process variations. Hence, there is a need to devise countermeasures which do not depend completely on detection. In order to achieve such a countermeasure, we propose to neutralize the effect of Hardware Trojans through redundancy. In this work, we present a Triple Modular Redundancy (TMR) based methodology to neutralize Hardware Trojans. In order to address the inevitable overhead on area, TMR will be implemented only on select paths of the circuit. Using a probabilistic model of a given digital circuit, we have measured the effect of Trojan on different paths of the circuit and found that equally probable output paths are vulnerable to Trojan placement. Therefore for security we propose that TMR should be implemented on the paths that lead to equally probable primary outputs. We have also shown that the detection of Trojans placed on predictable paths can be achieved through logic based testing methods. In order for the adversary to beat the proposed redundancy model, the size of the Trojan has to be larger. We have shown that such implementation can be detected using side channel based testing.     

Low-power fault-tolerant interconnect method based on LCDMA and duplication

High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a single wire using logic code division multiple access (LCDMA) technique. Reliability is increased by using hardware redundancy, and three LCDMA-based fault tolerant designs are proposed: (a) duplication with logic comparison (DLC), (b) conventional triple modular redundancy (TMR), and (c) triple modular redundancy with sign voter (TSV). With aim to detect a received bit from chip sequence, LCDMA–DLC and LCDMA–TSV designs compare absolute values of the sums, while LCDMA–TMR compares only sign bits of the sums generated at the outputs of decoders. All proposed designs are implemented in FPGA and ASIC technologies. MATLAB simulation results show that increasing the length of spreading codes affects to an increase in reliability. A comparative analysis of the proposed fault tolerant designs in terms of hardware complexity, latency, power consumption and error detecting and correcting capability is conducted. It is shown that LCDMA–DLC design has lower hardware overhead and power consumption, with satisfactory better bit error rate (BER) performance, in comparison to LCDMA–TMR and LCDMA–TSV approach.     

相控阵雷达数据处理计算机双机冗余的设计方法

简要阐述了相控阵雷达中数据处理计算机双机冗余的特点，从雷达系统可靠性的角度对双机冗余进行了总体设计。结合软硬件实现数据处理计算机的双机冗余设计，给出了故障监测和系统切换的硬件与软件框图，分析了双机容错结构系统重构策略与过程。最后略述数据处理计算机双机冗余设计在相控阵雷达控制系统中的应用情况。     

三模冗余在ASIC设计中的实现方法

星载计算机系统处于空间辐照环境中,可能会受到单粒子翻转的影响而出错,三模冗余就是一种对单粒子翻转有效的容错技术。通过对三模冗余加固电路特点的分析,提出了在ASIC设计中实现三模冗余的2种方法。其一是通过Syno—psys的综合工具DesignCompiler对原设计进行综合,然后修改综合后的门级网表再次综合;其二是直接建立采用三模冗余加固的库单元。     

Optoelectronic time-of-flight design and the demonstration of anall-optical, stored program, digital computer

The recent demonstration of an all-optical, stored-program, digital computer by our group focused on high-speed optoelectronic design. It was made possible by a new digital design method known as time-of-flight design. A rudimentary, but general-purpose, proof of principle computer was built, which is all-optical in the sense that all signals connecting logic gates and all memory are optical in nature. LiNbO₃ directional couplers, electrooptic switches, are used to perform logic operations. In addition to demonstrating stored program operation in an optoelectronic digital computer, the system demonstrated the feasibility of the new design method, which does nor use any flip-flops or other bistable devices for synchronization or memory. This potentially allows system clock rates of the same order as device bandwidth. This paper describes how the time-of-flight design method was motivated by the special properties of optoelectronic digital design. The basic principles of the method we employed will be discussed along with some of its potential advantages. The experimental work with digital optical circuits leading up to and including the stored program computer experiment will then be discussed. Finally, the future potential of time-of-flight design in high-bandwidth optoelectronic systems will be discussed     

Fault-Tolerant ICs: The Reliability of TMR Yield-Enhanced ICs

The use of triple modular redundancy (TMR) for reliability enhancement is well known. This paper presents a simple method' for predicting the reliability of integrated circuits (ICs) which use TMR for yield enhancement. A simple yield-model is included as it is necessary to factor in the effect of consumption of redundancy paths due to wafer fabrication defects. TMR implementation is briefly discussed as well.     

Design,evaluation and fault-tolerance analysis of stochastic FIR filters

Stochastic computing utilizes compact arithmetic circuits that can potentially lower the implementation cost in silicon area. In addition, stochastic computing provides inherent fault tolerance at the cost of a less efficient signal encoding. Finite impulse response (FIR) filters are key elements in digital signal processing (DSP) due to their linear phase-frequency response. In this article, we consider the problem of implementing FIR filters using the stochastic approach. Novel stochastic FIR filter designs based on multiplexers are proposed and compared to conventional binary designs implemented using Synopsys tools with a 28-nm cell library. Silicon area, power and maximum clock frequency are obtained to evaluate the throughput per area (TPA) and the energy per operation (EPO). For equivalent filtering performance, the stochastic FIR filters underperform in terms of TPA and EPO compared to the conventional binary design, although the stochastic design shows more graceful degradation in performance with a significant reduction in energy consumption. A detailed analysis is performed to evaluate the accuracy of stochastic FIR filters and to determine the required stochastic sequence length. The fault-tolerance of the stochastic design is compared with that of the binary circuit enhanced with triple modular redundancy (TMR). The stochastic designs are more reliable than the conventional binary design and its TMR implementation with unreliable voters, but they are less reliable than the binary TMR implementation when the voters are fault-free.     

A Unified Method for Analyzing Mission Reliability for Fault Tolerant Computer Systems

A reliability model is proposed and evaluated for a fault tolerant computer system which consists of multiple classes of modules and allows for degraded modes of performance. Each module of a given class has both an active and a passive hazard rate; constant hazard rates are assumed for active and dormant failures, and the given class may operate either in N Modular Redundancy (NMR: n + 1 out of 2n + 1 = N) or as a standby sparing system. The model allows for mission-phase changes at deterministic time points when the numbers of modules per class can be changed. The analysis proceeds by generalizing the notions of standby and NMR redundancy, which for N = 3 is TMR (Triple Modular Redundancy), into a concept called hybrid-degraded redundancy. The probabilistic evaluation of the unified redundancy concept is then developed to yield, for a given modular class, the joint distribution of success and the number of nonfailed modules from that class, at special times. With this information, a Markov chain analysis gives the reliability of an entire sequence of phases (mission profile).     

Fault-tolerant analysis of TMR design with noise-aware logic

Due to the effect of thermal noise, ground bounce and process variations in nanometer process, the behavior of any logical circuit becomes increasingly probabilistic. In this paper, based on the noise model [5] on the input and output nodes of a probabilistic CMOS (PCMOS) gate, the correctness probabilities of four PCMOS primitive gates, NOT, NAND, NOR and XOR, can be firstly computed. Based on the concept of the probabilistic transfer matrices (PTMs) and the corresponding operations on PTMs for the serial and parallel compositions of the components in a well-formed circuit, the correctness probability of the output in a 3-input PCMOS majority circuit in a triple modular redundancy (TMR) design can be further computed. For a given circuit with smaller error, it is well known that a TMR design has good fault-tolerant characterization and the correctness probability of the original output is converged to 1. Under the use of noise-aware logic in a TMR design, it is obvious that the fault-tolerant characterization of a TMR design is degraded and the correctness probability of the original output is not converged to 1. The experimental results show that the improvement region of the correctness probability of the original output will be narrowed due to the noise effect on the gates in a 3-input PCMOS majority circuit.     

Digital logic circuits

Recent progress in Josephson digital logic circuits is described. It is noted that changing the junction material from a lead alloy to niobium has dramatically improved process reliability, and that high-speed, low-power operations have been demonstrated at large-scale integrated-circuit levels. The first Josephson microprocessor, operated at 770 MHz, verified the potential of Josephson devices for future digital elements. The possibilities of the ultrafast Josephson computer, previously shelved because of a number of problems, are being actively reconsidered. The performance anticipated for Josephson digital circuits using high-temperature superconducting materials is also discussed     

The effect of compensating faults models on NMR system reliability

Realistic estimates of the reliability of systems with N-tuple modular redundancy (NMR), must consider the effect of compensation of logic faults. Earlier analyses that include compensating faults are impractical to use, yield very complex mathematical formulas for reliability indices, and/or concern the simplest triple modular redundancy (TMR) system only. This paper gives a general approach to the problem. Two models of compensating faults are considered. For either model the lower and upper bounds on frequency of compensating faults are found. By applying some results of NMR system evaluation, the new estimates of upper and lower bounds of NMR system reliability with respect to compensating faults are derived. A simple algebraic form of the final results makes them useful     

ADS—B系统应答的一种纠错算法设计与实现

ADS—B是基于ModeS数据链的一种技术,可以为传统雷达无法覆盖的区域提供监视服务。本文介绍了基于模式S的ADS—B系统基带数字信号处理流程,阐述了循环冗余编码（CRC）的工作原理。基于模式S的ADS-B系统,提出了一种基于循环冗余编码（CRC）的纠错算法;然后给出了纠错算法的FPGA实现方案,整个设计划分为多个功能...     

Maintainability Considerations in a Fault Tolerant/Faultproof Systems Design

The maintainability, reliability, and availability of a computer system are closely bonded to insure continuing service of a system. The ability of a system to tolerate failures or faults while operating is a principal requirement of a fault tolerant system. A fault tolerant system's design must incorporate considerations for maintenance and reliability in order to provide its ultimate requirement-available operation. These factors are considered in the design philosophy presented in this paper, identified as FAULTPROOF. FAULTPROOF design incorporates redundancy, reliability, maintainability, and adaptability to augment normally accepted fault tolerant design. The design approach described utilizes a hierarchical interconnection mechanism, Intelligent Networked Partitioning, to isolate faulted components.     

An efficient approach for multiple criteria redundancy optimization problems

The present paper provides an efficient approach to multiple criteria redundancy optimization problems, often encountered in reliability design of engineering systems. A search technique introduced earlier [10,11] in combination with the multicriteria optimization methods, based on min-max concept for finding Pareto optimal solution of multicriteria optimization problems, provides an efficient and excellent approach for solving redundancy optimization problems. The approach is illustrated through several numerical examples. Further, based on this approach, a very general computer code called ESMOP (Efficient Search Multi-Objective Programming) has also been developed. It is capable of considering any type of redundancy, constraint or individual cost function and thus offers to solve many reliability design problems.     

一种具有TSC功能的TMR系统表决器设计方法

本文给出了一种具有完全臬校验功能的三模冗余系统表决器的设计方法。与以往有关ＴＭＲ自温度方面的研究相比，此电路是完全自校验的，它直接将表决器做成完全自校验的，不用在系统外另加冗余四阶累积量适于ＶＬＳＩ实现，此设计思想很容易扩展成Ｎ模冗余系统完全自校验表决器的设计。     

光纤通信系统的可靠性分析及其计算机辅助设计

本文分析了光纤通信系统中元器件的可靠性,给出了光发射机备份冗余系统的计算机辅助设计方法。     

Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits

Due to the shrinking of feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, interference from radiation and noise-related transient faults. Many of these faults are not permanent in nature but their occurrence can result in malfunctioning of circuits, either due to complexity of digital circuits or due to interaction with software. A fault-tolerant scheme such as triple-modular redundancy (TMR) is being implemented increasingly in digital systems. One of the drawbacks of this scheme is that the reliability of the voter circuit is assumed to be very high, which may not be true. Most of the implementation of digital circuits is in the form of integrated circuit; so all the circuit elements are fabricated with same technology and hence reliability of all the components is usually same. In this paper we are presenting a novel fault-tolerant voter circuit which itself can tolerate a fault and give error free output by improving the overall system’s reliability.     

精密压力测试仪

针对洗衣机用水位传感器质量检测中存在的问题,开发了基于CAN(Controller Area Network)总线的精密压力检测系统。在上位计算机与前端测控模块之间的通信中,采用现场总线CAN网络技术。由于实现了系统冗余,系统具有安全可靠、功能完善、操作简便、性能价格比高等优点,成功实现了洗衣机用水位传感器检测的自动化,取得了较好的经济效益。