An accurate on-wafer deembedding technique with application to HBTdevices characterization

An accurate deembedding technique for on-wafer measurements of an active device's S-parameter is presented in this paper. This deembedding technique accounts in a systematic way for effect of all parasitic elements surrounding the device. These parasitic elements are modeled as a four-port network. Closed-form equations are derived for deembedding purposes of this four-port network. The proposed deembedding technique was used to extract small-signal model parameters of a 2×25 μm emitter GaInP/GaAs heterojunction bipolar transistor device, and excellent agreement between measured and model-simulated S-parameter was obtained up to 30 GHz     

Broad-band three-port and four-port stripline ferrite coupled line circulators

The broad-band characteristics of a stripline ferrite coupled line (FCL) section are verified through measurements, for the first time. Subsequent simulations and measurements on a 17-GHz three-port circulator employing a stripline FCL section shows a 65% bandwidth, from 11.5 to 22.5 GHz. A four-port FCL circulator, which is a modification of that proposed earlier by Masur and Mrozowski and Queck and Davis is also realized by connecting the two lines together at the center of the FCL section, i.e. within the ferrite region. Compared to the four-port circulator consisting of an FCL section and a hybrid coupler, it has the advantage of much broader bandwidth. Simulations and measurements confirm its circulating behavior and also show a similar 65% bandwidth, from 12.0 to 23.5 GHz.     

A New Method of Synthesizing Matched Broad-Band TEM-Mode Three-Ports

A new method of synthesizing matched broad-band TEM-mode three-ports is presented. The three-ports consist of n sections in cascade with each section composed of two coupled lossless transmission lines of electrical length /spl theta/ and an intermediate resistor. The main object is to analyze and design broad-band unsymmetrical structures with the symmetrical three-port as a special and important case. The analysis of the three-port is performed by means of a more convenient four-port analysis. An even-odd-mode method is used and a new definition of the odd mode is introduced. This new definition considerably simplfies the treatment of unsymmetrical three-and four-ports with one half of the network identical to the other apart from an impedance scaling factor. The analysis yields two uncoupled two-ports in each mode. The even-mode networks are identical with cascaded quarter-wave impedance transformers while the odd-mode networks contain all the resistors. A new technique for their design is presented and a computer program for complete synthesis of hybrid three-ports has been worked out. Several experimental stripline three-ports were built. A three-section unsymmetrical (k=1.7) matched three-port showed a measured isolation better than 20 dB and a maximum VSWR of 1.3 from 5 to 12 GHz. The total loss of a four-section equal-power divider was 0.2dB, maximum VSWR 1.25, and minimum isolation 23 dB over the frequency range 2.5-12.0 GHz.     

0.7-dB Insertion-Loss D-Band Lange Coupler Design and Characterization in 0.13 μm SiGe BiCMOS Technology

Design, measurement, and characterization of a low-loss Lange coupler on Si-substrate up to 170 GHz are presented in this paper. How to determine the value of the even number of the strip lines according to the process design rules is illustrated carefully based on odd- and even-mode impedance theory and calculation. The deembedding procedures of GSG pads and 50 Ω termination resistors are illustrated in details. Simulation and measurement results indicate that the fabricated on-chip 50 Ω resistors can be used for characterization of four-port Lange coupler by two-port network analyzer within expected measurement errors. Measurement results show that the minimum insertion loss of 0.7 dB at central frequency of 140 GHz is achieved, which is in excellent agreement with simulated data.     

An improved model for ground-shielded CMOS test fixtures

An improved model for ground-shielded (GS) test fixtures is proposed. The proposed model provides more accurate device-under-test gap behavioral model than previous test-fixture models and takes into account the impedance of the ground return path. The new model is validated up to 25 GHz by comparing the model simulations with experimental measurements. The proposed model is applied to bulk-silicon- and sapphire-based GS test fixtures with different layouts. Furthermore, a large phase shift in the shield-based test-fixture forward transmission is reported in this study. Based on the results achieved, suggestions for deembedding method selection are given. Test fixtures were fabricated using a 0.35-/spl mu/m CMOS process and 0.5-/spl mu/m silicon-on-sapphire CMOS process.     

A general noise and S-parameter deembedding procedure for on-waferhigh-frequency noise measurements of MOSFETs

A general deembedding procedure using one “OPEN” and two “THRU” dummy structures for noise and scattering parameter deembedding based on cascade configurations is presented in this paper. This technique does not require any equivalent-circuit modeling of probe pads or interconnections. This deembedding procedure is valid for designs having interconnections with any kinds of geometries and for devices operated at frequencies of several tens of gigahertz     

Development of Integrated Broad-Band CMOS Low-Noise Amplifiers

This paper presents a systematic design methodology for broad-band CMOS low-noise amplifiers (LNAs). The feedback technique is proposed to attain a better design tradeoff between gain and noise. The network synthesis is adopted for the implementation of broad-band matching networks. The sloped interstage matching is used for gain compensation. A fully integrated ultra-wide-band 0.18-mum CMOS LNA is developed following the design methodology. The measured noise figure is lower than 3.8 dB from 3 to 7.5 GHz, resulting in the excellent average noise figure of 3.48 dB. Operated on a 1.8-V supply, the LNA delivers 19.1-dB power gain and dissipates 32 mW of power. The gain-bandwidth product of the UWB LNA reaches 358 GHz, the record number for the 0.18-m CMOS broad-band amplifiers. The total chip size of the CMOS UWB LNA is 1.37 times 1.19 mm².     

Broad-band MMICs based on modified loss-compensation method using 0.35-/spl mu/m SiGe BiCMOS technology

Using the concept of loss compensation, novel broad-band monolithic microwave integrated circuits (MMICs), including an amplifier and an analog multiplier/mixer, with LC ladder matching networks in a commercial 0.35-mum SiGe BiCMOS technology are demonstrated for the first time. An HBT two-stage cascade single-stage distributed amplifier (2-CSSDA) using the modified loss-compensation technique is presented. It demonstrates a small-signal gain of better than 15 dB from dc to 28 GHz (gain-bandwidth product=157 GHz) with a low power consumption of 48 mW and a miniature chip size of 0.63 mm² including testing pads. The gain-bandwidth product of the modified loss-compensated CSSDA is improved approximately 68% compared with the conventional attenuation-compensation technique. The wide-band amplifier achieves a high gain-bandwidth product with the lowest power consumption and smallest chip size. The broad-band mixer designed using a Gilbert cell with the modified loss-compensation technique achieves a measured power conversion gain of 19 dB with a 3-dB bandwidth from 0.1 to 23 GHz, which is the highest gain-bandwidth product of operation among previously reported MMIC mixers. As an analog multiplier, the measured sensitivity is better than 3000 V/W from 0.1 to 25 GHz, and the measured low-frequency noise floor and corner frequency can be estimated to be 20 nV/sqrt(Hz) and 1.2 kHz, respectively. The mixer performance represents state-of-the-art result of the MMIC broad-band mixers using commercial silicon-based technologies     

Broad-Band Design Techniques for Transimpedance Amplifiers

In this paper, a novel bandwidth enhancement technique based on the combination of capacitive degeneration, broad-band matching network, and the regulated cascode (RGC) input stage is proposed and analyzed, which turns the transimpedance amplifier (TIA) design into a fifth-order low-pass filter with Butterworth response. This broad-band design methodology for TIAs is presented with an example implemented in CHRT 0.18-mum 1.8-V RF CMOS technology. Measurement data shows a -3-dB bandwidth of about 8 GHz with 0.25-pF photodiode capacitance. Comparing with the core RGC TIA without capacitive degeneration and broad-band matching network, this design achieves an overall bandwidth enhancement ratio of 3.6 with very small gain ripple. The transimpedance gain is 53 dBOmega with a group delay of 80plusmn20 ps. The chip consumes only 13.5-mW dc power and the measured average input-referred noise current spectral density is 18 pA/radicHz up to 10 GHz     

Extraction of substrate parameters for RF MOSFETs based on four-port measurement

In this work, a new method for extracting substrate parameters of radio frequency (RF) metal oxide semiconductor field effect transistors (MOSFETs) based on four-port measurement is presented. A T-liked substrate resistance network is used and the values of all components in the cold MOSFETs were extracted directly from the four-port data between 250 MHz and 8.5 GHz. The output admittance Y/sub 22/ can be well modeled up to 26.5 GHz based on the extracted substrate resistances and the other extrinsic capacitances extracted from an active device.     

A New Lossy Substrate Model for Accurate RF CMOS Noise Extraction and Simulation With Frequency and Bias Dependence

A lossy substrate model is developed to accurately simulate the measured RF noise of 80-nm super-100-GHz f_T n-MOSFETs. A substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1-18-GHz regime, which did not follow the typical thermal noise theory. Good match with the measured S-parameters, Y-parameters, and noise parameters before deembedding proves the lossy substrate model. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate deembedding using circuit simulation. The accuracy has been justified by good agreement in terms of I_d,g_m, Y-parameters, and f _T under a wide range of bias conditions and operating frequencies. Both channel thermal noise and resistance induced excess noises have been implemented in simulation. A white noise gamma factor extracted to be higher than 2/3 accounts for the velocity saturation and channel length modulation effects. The extracted intrinsic NF_min as low as 0.6-0.7 dB at 10 GHz indicates the advantages of super-100 GHz f_T offered by the sub-100-nm multifinger n-MOSFETs. The frequency dependence of noise resistance R_n suggests the bulk RC coupling induced excess channel thermal noise apparent in 1-10-GHz regime. The study provides useful guideline for low noise and low power design by using sub-100-nm RF CMOS technology     

Broad-band high-power amplifier using spatial power-combining technique

High power, broad bandwidth, high linearity, and low noise are among the most important features in amplifier design. The broad-band spatial power-combining technique addresses all these issues by combining the output power of a large quantity of microwave monolithic integrated circuit (MMIC) amplifiers in a broad-band coaxial waveguide environment, while maintaining good linearity and improving phase noise of the MMIC amplifiers. A coaxial waveguide was used as the host of the combining circuits for broader bandwidth and better uniformity by equally distributing the input power to each element. A new compact coaxial combiner with much smaller size is investigated. Broad-band slotline to microstrip-line transition is integrated for better compatibility with commercial MMIC amplifiers. Thermal simulations are performed and an improved thermal management scheme over previous designs is employed to improve the heat sinking in high-power application. A high-power amplifier using the compact combiner design is built and demonstrated to have a bandwidth from 6 to 17 GHz with 44-W maximum output power. Linearity measurement has shown a high third-order intercept point of 52 dBm. Analysis shows the amplifier has the ability to extend spurious-free dynamic range by N/sup 2/3/ times. The amplifier also has shown a residual phase floor close to -140 dBc at 10-kHz offset from the carrier with 5-6-dB reductions compared to a single MMIC amplifier it integrates.     

On the Deembedding Issue of CMOS Multigigahertz Measurements

The purpose of this paper is to address the issues of deembedding multigigahertz CMOS measurements by extensively comparing six popular methods and by proposing a new method based on two-port measurements. The comparison aims to evaluate the maximum applicable frequency of equivalent-circuit methods (open-short, three step, ...) and the effect of the source dangling leg of MOSFETs on the cascade methods (two line and thru). Fifty dummy structures and 12 MOSFETs were fabricated using standard 0.18-mum CMOS technology. It was found that, at low frequencies (<6 GHz), all method results were comparable. The open-short method performed well over the entire frequency range (0.1-40 GHz) studied. The newly developed method, called the thru-short method, uses only two dummy structures, a thru and a short, to completely deembed the parasitics from probe pads, interconnects, and the semiconducting substrate. The measurements validated the thru-short algorithm and showed its usefulness for multigigahertz on-wafer CMOS measurements.     

A 1-17-GHz InGaP-GaAs HBT MMIC analog multiplier and mixer with broad-band input-matching networks

An InGaP-GaAs heterojunction bipolar transistor (HBT) analog multiplier/mixer monolithic microwave integrated circuit (MMIC) is developed that adopts a Gilbert-cell multiplier with broad-band input-matching networks to widen the bandwidth up to 17 GHz. This MMIC was fabricated using a commercially available 6-in InGaP-GaAs HBT MMIC process. It achieved a measured sensitivity of above 1100 V/W for an analog multiplier and a conversion gain of better than 9 dB for a mixer. It also demonstrated a lower corner frequency and noise than that of an InP HBT analog multiplier. The measured low-frequency noise was 10 nV/sqrt(Hz), which is about half of that of an InP HBT analog multiplier with a similar architecture. The corner frequency of the low-frequency noise was roughly estimated to be 15 kHz. The measured performance of this MMIC chip with gain-bandwidth-product (GBP) of 47 GHz rivals that of the reported GaAs-based analog multipliers and mixers. The high GBP result achieved by this chip is attributed to the HBT device performance and the broad-band input-matching network.     

A Low-Noise 47-GHz Mixer Using a Permanent Josephson Junction

A new method to produce permanent Josephson junctions for millimeter-wave mixers is reported. In contrast to conventional point contacts which are mechanically unstable and require adjustments after each cooldown, these point contact junctions are set at room temperature, stay mechanically stable, and can be temperature cycled without readjustments. Using these junctions in a modified Sharpless wafer mixer mount, a single-sideband noise temperature of 71 K was measured at 47 GHz. Based on these results, system noise temperatures of less than 100 K are predicted for practical broad-band radiometers, RADAR, and communications receivers up to at least 100 GHz     

A Novel Broad-Band MMIC VCO Using an Active Inductor

This paper proposes a novel broad-band MMIC VCO using an active inductor. This VCO is composed of a serial resonant circuit, in which the capacitor is in series with an active inductor that has a constant negative resistance. Since the inductance value of this active inductor is inversely proportional to the square of the transconductance and can vary widely with the FETs gate bias control, a broad-band oscillation tuning range can be obtained. Furthermore, since this active inductor can generate a constant negative resistance of more than 50 , the proposed VCO can oscillate against a 50- output load immediately without using additional impedance transformers. We have fabricated the VCO using a GaAs MESFET process. A frequency tuning range of more than 50%, from 1.56 to 2.85 GHz, with an output power of 4.4±1.0 dBm, was obtained. With a carrier of 2.07 GHz, the phase noise at 1-MHz offset was less than –110 dBc/Hz. The chip size was less than 0.61 mm², and the power consumption was 80 mW. This broad-band analog design can be used at microwave frequencies in PLL applications as a compact alternative to other types of oscillator circuits.     

Multioctave spatial power combining in oversized coaxial waveguide

We describe a multioctave power-combiner structure using finline arrays in an oversized coaxial waveguide. The spectral-domain method (SDM) is used to compute the propagation constant in this structure, and is verified with HFSS simulations. The SDM method is then employed to synthesize broad-band tapered impedance transformers in finline for coupling energy to and from a set of monolithic microwave integrated circuit (MMIC) amplifiers. A modular assembly is described using a sectoral tray architecture. The concept is demonstrated for a 32-MMIC system using low-power traveling-wave amplifier MMICs, providing a 3-dB bandwidth of 13 GHz (3-16 GHz). An output combining loss of 1 dB is estimated from the small-signal measurements, suggestion a combining efficiency of ~75% for 32 MMICs     

A Nonlinear Electro-Thermal Scalable Model for High-Power RF LDMOS Transistors

A new nonlinear charge-conservative scalable dynamic electro-thermal compact model for laterally defused MOS (LDMOS) RF power transistors is described in this paper. The transistor is characterized using pulsed I–V and S-parameter measurements, to ensure isothermal conditions. A new extrinsic network and extrinsic parameter-extraction methodology is developed for high-power RF LDMOS transistor modeling, using manifold deembedding by electromagnetic simulation, and optimization of the extrinsic network parameter values over a broad frequency range. The intrinsic model comprises controlled charge and current sources that have been implemented using artificial neural networks, designed to permit accurate extrapolation of the transistor's performance outside of the measured data domain. A thermal sub-circuit is coupled to the nonlinear model. Large-signal validation of this new model shows a very good agreement with measurements at 2.14 GHz.      

Design and Performance Analysis of an Octave Bandwidth Waveguide Mixer

A new broad-band mixer capable of operating over two full adjacent waveguide bands (18 to 26.5 GHz and 26.5 to 40 GHz) is described. Within the octave bandwidth from 20 to 40 GHz, the maximum conversion loss is 6.5 dB with a corresponding average DSB noise figure of 5.7 dB. A theoretical analysis is given to treat quantitatively the performance of the octave bandwidth waveguide mixer.