3D-IC中基于时分复用的TSV蜂窝容错设计

三维芯片(3D-IC)通过硅通孔(TSV)技术来实现电路的垂直互连,延续了摩尔定律,但在制造、绑定等过程中,TSV容易引入各类缺陷。添加冗余TSV是解决该问题的有效方法之一,但TSV面积开销大、制造成本高。提出一种基于时分复用(TDMA)的TSV蜂窝结构容错设计方案,它基于时间对信号TSV进行复用。实验结果表明,与一维链式TDMA结构相比,蜂窝TDMA结构提高了30%的故障覆盖率,并且故障覆盖率随着蜂窝阵列的扩展持续提升。在64TSV阵列中,与一维TDMA结构相比,蜂窝拓扑结构的面积开销降低了10.4%。     

三维片上网络故障及拥塞感知的容错路由器设计

 三维片上网络中路由器的输入端口和交叉开关出现故障,将严重影响整个网络的性能,因此文章提出了一种故障及拥塞感知的容错路由器.通过增加一个冗余的输入端口和旁路总线,不仅能实现对输入端口和交叉开关容错的目的,而且还能在没有端口故障的情况下使用冗余端口有效地解决拥塞问题.实验表明此容错机制能够使得网络在故障路由器多、拥塞严重的情况下,仍然保持良好的性能.     

WiNoC中无线通信拥塞与故障感知的容错路由算法

在无线片上网络中,无线通信拥塞和故障对整个片上网络的通信效率具有严重影响.为此本文提出了一种针对无线通信拥塞和故障的容错路由算法,首先设计了无线通信拥塞和故障感知模型,该模型能够感知无线节点通信对的拥塞和故障信息,并对其编码发送给子网中的路由器;然后子网中的路由器根据接收到的无线节点通信对状态信息,判断数据包是否使用无线传输.实验表明,本文方案相较于对比对象能够在较小的额外面积、功耗开销下,保证较低的网络延迟和较高的网络吞吐率,并对无线节点通信对的永久性故障具有良好的容错能力.     

基于网络监控器的专用片上网络动态容错路由

针对专用片上网络（Network on Chip,NoC）全局通信事务管理和可靠性设计问题,提出片上网络监控器的概念,用于获取全局网络实时状态信息及执行路径分配算法,基于此提出一种动态路由机制DyRS-NM.该机制能检测和定位NoC中的拥塞和故障链路,并能区分瞬时和永久性链路故障,采用重传方式避免瞬时故障,通过重新路由计算绕开拥塞和永久性故障.设计实现了RTL级网络监控器和与之通信的容错路由器模块,并将MPEG4解码器应用映射至基于网络监控器的4×4Mesh结构NoC体系结构中,验证了系统性能以及面积功耗开销.相比静态XY路由和容错动态路由FADR,DyRS-NM机制在可接受的开销代价下获得了更优的性能.     

接口标记容错路由算法

随着片上系统(SoC)集成度的不断提高,IP核之间的通信故障成为亟待解决的问题,片上网络(NoC)是解决SoC通信问题的有效途径。容错路由算法是NoC设计中的关键技术,对NoC的通信效率有重要影响。在Valiant随机路由算法和源路由算法的基础上,提出了一种接口标记容错路由算法。该算法吸取了Valiant随机路由算法能平衡网络负载、降低拥塞概率的优良性能与源路由算法中路径不需要计算与查找的特点,减小了传输时延,提高了路由器的利用率。     

Motorola智能动态时钟驱动器

Motorola推出业界首批智能动态时钟驱动器系列产品,为需要多重(redundant)故障保护的系统提供了首屈一指的时钟解决方案。新推出的智能时钟解决方案系列采用Motorola的硅锗工艺制造,为设计者提供了经济高效的单片解决方案。这些解决方案可提供高性能和集成多重功能,将显著提高下一代计算机、服务器、通信和网络设备所需的系统可靠性。时钟驱动器是关键的系统部件,能够为包括计算机、电信、网络路由和交换设备在内的多种通信设备同步和分布数据信号。智能动态时钟交换机(IDCS)系列能够满足高性能计算机、联网和电信应用领域内最严格的要求…     

一种面向应用的NoC容错路由算法

随着芯片集成度的不断提高,芯片制造工艺进入深亚微米级以后,片上将会出现更多难以预测与消除的故障类型。为了实现可靠的片上通信,应用容错机制与算法是一个重要的解决方案。本文提出一种面向应用的NoC容错路由算法,该算法在重负载时使用带有部分故障的链路并使流量在网络中均匀分布。同时给出了实现该算法需要的扩展后的路由器结构。仿真结果表明,所提出的路由算法与现有的路由算法相比,具有更好的时延性能。     

基于内建自测技术的Mesh结构NoC无虚通道容错路由算法

 在Zhang's算法绕行思想的基础上,提出了一种2D-Mesh结构片上网络无虚通道容错路由算法,用于解决多故障节点情况下片上网络的无虚通道容错路由问题.算法利用内建自测试机制获取故障区域的位置信息,通过优化绕行策略来均衡故障区域周围链路的负载并减少部分数据的绕行距离.针对8×8的2D-Mesh网络的仿真表明,与Chen's算法相比,在故障区域大小为2×2,网络时延为70 cycles的情况下,随着故障区域位置的变化所提算法可提高1.2%到4.8%的网络注入率.且随着故障区域面积的扩大,所提算法在减少通信时延,提高网络吞吐量方面的作用更为明显.     

面向性能优化的可重构片上网络技术研究

片上网络已经成为众核时代最具潜力的片上互连解决方案.然而,现有片上网络灵活性不足,无法支持通信的动态行为.研究具有高度灵活性、适应性和可配置性的可重构片上网络,对于提高复杂应用的通信效率具有重要意义.介绍了可重构片上网络的研究背景和相关研究,提出了一个面向可重构片上网络的系统化研究框架,阐述了可重构片上网络的重要研究点,给出了相关研究结果及实验数据.     

基于重构的片上网络容错机制

为了保证片上网络的可靠性,本文提出了一种新的容错机制。在片上网络中由于路由器故障将导致与其连接的IP核不能与其他核通信,使片上网络的可靠性降低。本文的方法通过选择最优相邻的路由器来替代故障路由器,从而达到恢复IP核通信的目的。通过为每个路由器配置一个状态寄存器,用来存储相邻路由器的安全度,在路由时采用新的可重构路由算法绕过故障的路由器,以提高片上网络的可靠性。在OPNET平台上对5×52D-Mesh结构的片上网络进行仿真实验,统计了数据传输延时。试验结果表明,本文提出的路由算法与对比文献的路由算法相比,在延迟方面有明显的优势。     

面向通信能耗的3D NoC映射研究

对于传统的平面结构,三维片上网络(3D NoC)具有更好的集成度和性能,在单芯片内部可以集成更多的处理器核。3D NoC作为2D NoC的结构拓展,在性能提高和低功耗设计方面更具优越性,成为多核系统芯片结构的主流架构。映射就是应用某种算法寻找一种最优方案,将通信任务图的子任务分配到NoC的资源节点上,保证NoC的通信能耗最小。参照2D NoC的研究方法,提出了针对3D网格NoC的通信能耗模型,采用蚁群算法实现了面向通信能耗的NoC映射。实验结果表明,面向不同网络规模的3D网格NoC平台,蚁群映射同随机映射相比,通信能耗降低可以达23%～42%。     

An interconnection architecture for network-on-chip systems

Network on Chip (NoC) is a discipline research path that primarily addresses the global communication in System on Chip (SoC). It is inspired and uses the same routing and switching techniques needed in multi-computer networks. Current shared-bus based on-chip communication architectures generally have limited scalability due to the nature of the buses especially when complex on-chip communication SoC is needed. The main goal is to have a dedicated communication infrastructure in the system that can scale up while minimizing the area and power. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we introduce a new NoC architecture by adapting a recursive topology structure. An experimental study is performed to compare this structure with basic NoC topologies represented by 2D mesh and Spidergon. The analysis illustrates the main features of this topology and its unique benefits. The simulation results show that recursive network outperforms 2D mesh and Spidergon in main performance metrics.     

3-D Topologies for Networks-on-Chip

Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumption models of these novel 3D structures. An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed. Tradeoffs between the number of nodes utilized in the third dimension, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the functional blocks of the network, which decreases the length of the communication channel, is evaluated for both the latency and power consumption of a network. A performance improvement of 40% and 36% and a decrease of 62% and 58% in power consumption is demonstrated for 3D NoC as compared to a traditional 2D NoC topology for a network size of N = 128 and N = 256 nodes, respectively.     

基于片上网络众核系统容错技术研究

基于片上网络的众核系统已经广泛应用在各个领域之中.用户对系统性能和系统可靠性的需求越来越高.文中对众核系统和片上网络容错技术基础进行介绍,针对众核系统软错误和硬错误分析现有的几种典型的众核系统冗余容错方法,比较了其性能差异.在总结了现有技术不足的基础上进一步分析了该领域未来的研究趋势.     

A Simple BCH Decoder for NoC Interconnects and SoC Buses

Network on a chip (NoC) uses packet-switched network to implement interconnections in System on chip (SoC). In SoC design, performance and energy efficiency are respectively the first and second priorities, and optimal on-chip communication should decrease the power consumption and area overhead. In this work, a simplified BCH codec is proposed for reliable communication in NoC and SoC. It performs BCH error corrections without Berlekamp's algorithm, only using reduced syndrome bits to determine error patterns. The error locations can be found by looking up tables, by which the possible errors are directly corrected. Only one matrix product and one ROM access are required in the BCH decoder. The proposed (20, 8, 2) and (31, 16, 3) decoders in the paper can be easily applied for error corrections of interconnects and buses for NoC and SoC. It is also beneficial to correct data lines without length definition and controllines without storage.     

High-level customization framework for application-specific NoC architectures

Network-on-Chip (NoC) has been recognized as the new paradigm to interconnect and organize a high number of cores. NoCs address global communication issues in System-on-Chips (SoC) involving communication-centric design and implementation of scalable communication structures evolving application-specific NoC design as a key challenge to modern SoC design. In this paper we present a SystemC customization framework and methodology for automatic design and evaluation of regular and irregular NoC architectures. The presented framework also supports application-specific optimization techniques such as priority assignment, node clustering and buffer sizing. Experimental results show that generated regular NoC architectures achieve an average of 5.5 % lower communication-cost compared to other regular NoC designs while irregular NoCs proved to achieve on average 4.5×higher throughput and 40 % network delay reduction compared to regular mesh topologies. In addition, employing a buffer sizing algorithm we achieve a reduction in network’s power consumption by an average of 45 % for both regular and irregular NoC design flow.     

基于云进化算法的3D NoC测试端口优化选择

针对于三维片上网络测试时,如何选择测试端口以提高测试效率的难题,采用基于云模型的进化算法对三维片上网络测试端口进行位置寻优,并对IP核的测试数据进行合理分配,在测试功耗约束条件下,以重用片上网络作为测试访问机制,基于XYZ路由算法和非抢占式测试调度方式,对三维片上网络IP核实施并行测试,以提高测试效率。研究结果表明,该方法可对测试端口的位置及组合方案进行精确寻优,且有效减少了测试时间。     

3D NoC测试规划研究与实现

针对3D NoC资源内核的测试,采用NoC重用测试访问机制和XYZ路由方式,建立功耗模型,并通过云进化算法将IP核的测试数据划分到各TAM上进行并行测试,从而降低了测试时间。实验以ITC 02标准电路作为测试对象,其结果表明,文中方法可以有效地减少测试时间,提高了测试效率。     

不规则2D Mesh NoC映射算法研究

片上网络(NoC)因其分层通讯结构而有望成为未来动态重构片上系统的支撑技术,针对复杂片上系统中可能集成各种规模IP的实际情况,对不规则2D mesh拓扑结构的NoC进行了研究,建立了其映射算法的数学模型和优化目标函数,提出了保证网格不重叠约束条件的数学表达和IP间通信距离的求解方法,采用一个视频解码器实例,给出了映射算法模拟结果和分析,并探讨了布局结果的FPGA实现.