Low voltage second-order alpha function synapse

This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental input resistance in the ohmic range, for input signals in the microampere range, such as are encountered in the design of instrumentation for electrochemical ampero-metric sensors, optical-sensing and current-mode circuits. This low input-resistance is achieved using an input stage incorporating negative feedback. In a Cadence simulation of an exemplary design using a 180 nm CMOS process and operating with?±?1.8 V supply rails, the input resistance is 1.05 ohms and the power dissipation is 93.6 µW. The bandwidth, for a gain of 100 dBohm, exceeded 9 MHz. For a 1µA, 1 MHz sinusoidal input signal the Total Harmonic Distortion, with this gain, is less than 1%. The input referred noise current with zero photodiode capacitance is 2.09 pA/√Hz and with a photodiode capacitance of 2pF is 8.52 pA/√Hz. Graphical data is presented to show the effect of a photodiode capacitance varying from 0.5 to 2 pF, when the TIA is used in optical sensing. In summary, the required very low input resistance, at a low input current level (µA) is achieved and furthermore a Table is included comparing the characteristics and a widely used Figure of Merit (FOM) for the proposed TIA and similar published low-power TIAs. It is apparent from the Table that the FOM of the proposed TIA is better than the FOMs of the other TIAs mentioned.

     

Design of broadband transimpedance amplifier for optical communication systems

This paper describes the design and analysis of broadband transimpedance amplifiers (TIAs) based on Regulated Cascode (RGC) configuration. The focus is to deal with bandwidth restriction occurring in optical receivers coming from TIA input parasitic capacitances. Despite the conventional method for broadband RGC TIA design that a ladder matching network is employed to isolate the input capacitance of TIA and the photodiode capacitance, the proposed TIA eliminates the effects of these parasitic components by absorbing them in a T-matching network. The conventional broadband RGC TIA is analyzed and the disadvantages of the ladder matching network is demonstrated in a TIA design example. The proposed RGC TIA is simulated on 0.18-μm standard RF CMOS process. The simulation results presented show that the Gain-Bandwidth product (GBW) is extended by a larger factor compared to that of the conventional broadband RGC TIA while the biasing conditions and the value of the photodiode capacitance are considered the same.     

Area-efficient CMOS transimpedance amplifier for optical receivers

In this letter, a broadband area-efficient transimpedance amplifier (TIA) for optical receivers is designed using a standard 0.18 μm CMOS technology. A new shunt–shunt peaking technique is used at the input transimpedance stage, which is followed by a gain stage and a capacitive degeneration stage. The amplifier achieves a wide bandwidth with only one inductor; hence a smaller silicon area is maintained. The proposed TIA has a measured transimpedance gain of 50 dB Ohm and a −3 dB bandwidth of 6.5 GHz for 0.25 pF input photodiode capacitance. It consumes DC power of 14 mW from a 1.8 V supply voltage and occupies only 0.09 mm² silicon area.     

1Gb/s CMOS调节型共源共栅光接收机

基于特许0.35μm EEPROM CMOS标准工艺设计了一种单片集成光接收机芯片,集成了双光电探测器(DPD)、调节型共源共栅(RGC)跨阻前置放大器(TIA)、三级限幅放大器(LA,limiting amplifier)和输出电路,其中RGCTIA能够隔离光电二极管的电容影响,并可以有效地扩展光接收机的带宽。测试结果表明,光接收机的3dB带宽为821MHz,在误码率为10-9、灵敏度为-11dBm的条件下,光接收机的数据传输速率达到了1Gb/s;在3.3V电压下工作,芯片的功耗为54mW。     

6 GHz transimpedance amplifier for optical sensing system in low-cost 0.35 /spl mu/m CMOS

A high-speed transimpedance amplifier (TIA) has been designed and implemented in a low cost 0.35 mum CMOS technology. Combining the techniques of regulated cascode input stage, current shunt feedback and inductive-series peaking, the TIA achieves a transimpedance gain of 51 dBOmega and 3 dB bandwidth of 6 GHz, in the presence of a photodiode capacitance of 0.6 pF. This is believed to be the fastest TIA ever reported in 0.35 mum CMOS technology     

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS tech nology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capaci tance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resis tance is 50 Ω, and the average input noise current spectral density is 9.7 pA/(Hz)~(1/2). Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.     

1-Gb/s 80-dB/spl Omega/ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects

A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-/spl mu/m standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dB/spl Omega/ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-/spl mu/A average input noise current, -17-dBm sensitivity for 10/sup -12/ bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels.     

1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.     

A CMOS imaging diversity receiver for gigabit free-space optical MIMO

A 7-channel imaging diversity receiver based on current-summing is implemented in a 180 nm CMOS technology for broadband free-space optical (FSO) multi-input/multi-output (MIMO) communication. Each channel employs a low input-impedance current mirror (CM) as the input stage, which allows the implementation of direct current-summing for equal-gain combining (EGC). The summed current signal drives a second stage transimpedance amplifier (TIA) to generate the output voltage. Electrical characterization was performed using a photodiode emulation circuit and chip-on-board FR-4 assembly, demonstrating a total transimpedance gain of 62 dBΩ, −3 dB bandwidth of 1.2 GHz, and eye diagrams up to 2 Gb/s for 0.25 pF photodiode capacitance. The theoretical sensitivity of the imaging receiver is −16.8 dBm for a bit error rate (BER) of 10⁻⁹ at a photodetector responsivity of 0.4 A/W. The simulated power consumption for a single front-end amplifier circuit is 4.2 mW, and for the second stage TIA is 10.3 mW from a single 1.8 V supply. The diversity receiver is flip-chip compatible to enable hybrid integration to a custom InGaAs photodetector array.     

A 40 Gbit/s fully integrated optical receiver analog front-end in 90 nm CMOS

A fully integrated 40 Gbit/s optical receiver analog front-end (AFE) including a transimpedance amplifier (TIA) and a limiting amplifier (LA) for short distance communication is described in this paper.The proposed TIA employs a modified regulated cascode (RGC) configuration as input stage,and adopts a third order interleaving active feedback gain stage.The LA utilizes nested active feedback,negative capacitance,and inductor peaking technology to achieve high voltage gain and wide bandwidth.The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV(p p).Simulation results show that the receiver AFE provides conversion gain of up to 83 and bandwidth of 34.7 GHz,and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA(rms).     

High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS

The design and measurement of two optical receivers with integrated photodiode in 130 nm CMOS is presented. The low bandwidth, which is typical for photodiodes in CMOS technologies, is circumvented by a differential photodiode topology on the one hand and by including an optimized equalizer in the receiver chain on the other hand. The low responsivity of a CMOS photodiode is compensated by a very low-noise design for the differential TIA. The disadvantage of such a low-noise design is its high power consumption. Therefore, a design strategy is presented where part of the circuit is biased in weak inversion. Doing so, the power consumption is decreased from 138 mW for the standard design to only 74.16 mW. Both designs are measured optically with 850 nm modulated light and are able to operate at 4.5 Gbit/s with a BER lower than 10^-12. The sensitivities for this BER and speed are - 3.8 dBm and -3.4 dBm respectively. The receivers even work up to 5 Gbit/s for BER values around 10^-9.     

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.     

A 122 TΩ Hz transimpedance bandwidth product BiCMOS optical sensor front-end with a 54.7 dB voltage-controlled photo-sensitivity range

An optical sensor front-end with integrated PIN photodiode in 0.6 μm BiCMOS technology intended for universal optical storage operation is presented. It is based on a mixed current conveyor and voltage amplifiers topology avoiding stability problems. The transimpedance is continuously variable and directly proportional to a voltage-controlled resistance. Another voltage-controlled resistor within a variable-gain voltage amplifier increases the photo-sensitivity range. A fixed-gain voltage amplifier and a current biasing of the current conveyor enable frequency bandwidth enhancement leading to a large transimpedance bandwidth product. A linearity error smaller than 2.8%, a photo-sensitivity range of 541 (54.7 dB) with the largest photo-sensitivity of 2468 mV/μW, an offset voltage <13.7 mV, a frequency bandwidth up to 277 MHz, a slew rate up to 377 V/μs, a transimpedance bandwidth product up to 122 TΩ Hz, and a maximum power consumption of <4.3 mW are achieved.     

8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

This work presents the design and the measured performance of a 8 Gb/s transimpedance amplifier (TIA) fabricated in a 90 nm CMOS technology. The introduced TIA uses an inverter input stage followed by two common-source stages with a 1.5 kΩ feedback resistor. The TIA is followed by a single-ended to differential converter stage, a differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows a measured optical sensitivity of ?18.3 dBm for a bit error rate = 10^?9. A gain control circuitry is integrated with the TIA to increase its input photo-current dynamic range (DR) to 32 dB. The TIA has an input photo-current range from 12 to 500 μA without overloading. The stability is guaranteed over the whole DR. The optical receiver achieves a transimpedance gain of 72 dBΩ and 6 GHz bandwidth with 0.3 pF total input capacitance for the photodiode and input PAD. The TIA occupies 0.0036 mm² whereas the complete optical receiver occupies a chip area of 0.46 mm². The power consumption of the TIA is only 12 mW from a 1.2 V single supply voltage. The complete chip dissipates 60 mW where a 1.6 V supply is used for the output stages.     

Broad-Band Design Techniques for Transimpedance Amplifiers

In this paper, a novel bandwidth enhancement technique based on the combination of capacitive degeneration, broad-band matching network, and the regulated cascode (RGC) input stage is proposed and analyzed, which turns the transimpedance amplifier (TIA) design into a fifth-order low-pass filter with Butterworth response. This broad-band design methodology for TIAs is presented with an example implemented in CHRT 0.18-mum 1.8-V RF CMOS technology. Measurement data shows a -3-dB bandwidth of about 8 GHz with 0.25-pF photodiode capacitance. Comparing with the core RGC TIA without capacitive degeneration and broad-band matching network, this design achieves an overall bandwidth enhancement ratio of 3.6 with very small gain ripple. The transimpedance gain is 53 dBOmega with a group delay of 80plusmn20 ps. The chip consumes only 13.5-mW dc power and the measured average input-referred noise current spectral density is 18 pA/radicHz up to 10 GHz     

Low-power 10 Gb/s inductorless inverter based common-drain active feedback transimpedance amplifier in 40 nm CMOS

This study presents an inductorless 10 Gb/s transimpedance amplifier (TIA) implemented in a 40 nm CMOS technology. The TIA uses an inverter with active common-drain feedback (ICDF-TIA). The TIA is followed by a two-stage differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows measured optical sensitivities of ?17.7 and ?16.2 dBm at BER = 10^?12 for data rates of 8 and 10 Gb/s, respectively. The TIA has a simulated transimpedance gain of 47 dBΩ, 8 GHz bandwidth with 0.45 pF total input capacitance for the photodiode, ESD protection and input PAD. The TIA occupies 0.0002 mm² whereas the complete optical receiver occupies a chip area of 0.16 mm². The power consumption of the TIA is only 2.03 mW and the complete chip dissipates 17 mW for a 1.1 V single supply voltage. The complete optical receiver has a measured transimpedance gain of 57.5 dBΩ.     

Bandwidth enhancement for transimpedance amplifiers

A technique for bandwidth enhancement of a given amplifier is presented. Adding several interstage passive matching networks enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known low-pass filter component values, is introduced. To demonstrate the feasibility of the method, a CMOS transimpedance amplifier (TIA) is implemented in a 0.18-/spl mu/m BiCMOS technology. It achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5-pF photodiode capacitance. This corresponds to a bandwidth enhancement ratio of 2.4 over the amplifier without the additional passive networks. The transresistance gain is 54 dB/spl Omega/, while drawing 55 mA from a 2.5-V supply. The input sensitivity of the TIA is -18 dBm for a bit error rate of 10/sup -12/.     

InP-InGaAs single HBT technology for photoreceiver OEIC's at 40Gb/s and beyond

We describe an advanced InP-InGaAs-based technology for the monolithic integration of pin-photodiodes and SHBT-transistors. Both devices are processed using the same epitaxial grown layer structure. Employing this technology, we have designed and fabricated two photoreceivers achieving transimpedance gains of 170 Ω/380 Ω and optical/electrical bandwidths of 50 GHz/34 GHz. To the best of our knowledge, this is the highest bandwidth of any heterojunction bipolar transistor (HBT)-based photoreceiver optoelectronic integrated circuit (OEIC) published to date. We even predict a bandwidth of 60 GHz for the same circuit topology by a simple reduction of the photodiode diameter and an adjustment of the feedback resistor value     

High-Speed CMOS Integrated Optical Receiver With an Avalanche Photodetector

We present a high-speed monolithically integrated optical receiver fabricated with 0.13-mum standard complementary metal-oxide-semiconductor (CMOS) technology. The optical receiver consists of a CMOS-compatible avalanche photodetector (CMOS-APD) and a transimpedance amplifier (TIA). The CMOS-APD provides high responsivity as well as large bandwidth. Its bandwidth is further enhanced by the TIA having negative capacitance, which compensates undesired parasitic capacitance. With the CMOS integrated optical receiver, 4.25-Gb/s optical data are successfully transmitted with a bit-error rate less than 10^-12 at the incident optical power of - 5.5 dBm.     

Optical Receiver With Widely Tunable Sensitivity in BiCMOS Technology

A monolithically integrated optical receiver with voltage-controlled sensitivity in 0.6-m BiCMOS technology is presented. The transimpedance variations are achieved by varying the control voltage of the voltage-controlled resistor changing its equivalent resistance. The optical receiver design is based on a P-intrinsic-N photodiode and on a mixed current-mode and voltage-mode approach, by using a current conveyor and a voltage amplifier. Thanks to the current-mode signal processing, the bandwidth of the optical receiver is independent of the photodiode capacitance. A linearity error smaller than 2.92%, a sensitivity dynamic range of 83.2 (38.4 dB), an offset voltage smaller than 0.56 mV, a power consumption less than 4.7 mW, and a bandwidth up to 205.5 MHz are achieved.