A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates

In this paper, a new charging scheme for reducing the power consumption of dynamic circuits is presented. The proposed technique is suitable for large fan-in gates where the dynamic node discharges frequently. Simulation results demonstrate that the proposed method is efficiently controlling the internal voltage swing and hence decreasing the power consumption of the wide fan-in OR gate without sacrificing other circuit parameters such as gate speed, area or noise immunity. The power-delay product of a simulated 8-input OR gate is reduced by 46%, compared to its conventional dynamic counterpart in the 90 nm CMOS technology. Another important benefit of the proposed approach is 99X reduction in power dissipation of the gate load by limiting its switching activity. Furthermore, the delay of the proposed circuit experiences only 0.94% variation over 10% fluctuation in the threshold voltages of all transistors for a 32-bit OR gate. Using the proposed technique, a 40-bit tag comparator is simulated at 1 GHz clock frequency. The power consumption of the designed circuit is as low as 1.987 µW/MHz, while the delay and unity noise gain (UNG) of the circuit are 244 ps and 499 mV, respectively.     

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I_D=5 μA/μm and V_DS=0.5 V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V_DD=0.5 V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ～20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V_DD=0.5 V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ～10%, ～35% and ～25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.     

A new erase method for scaled NAND flash memory device

A suitable bird-beak thickness is crucial to the cell reliability. However, the process control for bird-beak thickness in the edge region is very difficult. A new erase method is proposed in this work to modulate the electron tunneling region of 40 nm floating gate NAND flash memory device. The erasing electron can move to gate center from gate edge under back bias at 0.3 V/− 0.8 V. The Fowler-Nordheim (FN) current of erase operation distributes on the whole channel region, not located at the gate edge region. Results show that the proposed method can improve cell reliability about 33%. TCAD analysis is employed to explain and prove the mechanism. This new erase method is promising for scaled NAND flash memory.     

Impact of source-to-drain tunnelling on the scalability of arbitrary oriented alternative channel material nMOSFETs

In this work, the scalability of alternative channel material double gate nano nMOSFETs has been investigated by the mean of semi-analytical models of I_on/I_off currents, accounting for quantum capacitance degradation, short channel effects, band-to-band and source-to-drain tunnelling in arbitrary substrate and channel direction.Contrary to most of the previous study neglecting source-to-drain tunnelling, it has been found that for devices with physical gate length below 13 nm (as required in the 22 and 16 nm nodes), this mechanism significantly penalises the I_on/I_off trade off of small effective masses channel materials like Ge or GaAs, much more than in the case of Si and biaxially strained Si (s-Si). In addition, only strained Si-MOSFETs has been found to meet the performance expectation of the International Technology Roadmap of Semiconductor for the 22 nm and 16 nm technological nodes.     

Low-power MicroVrms noise neural spike detector for implantable interface microsystem device

In this paper, an ultra-low-power and low-noise spike detector is proposed for massive integration in the implantable multichannel brain neural recording device. The detector circuit with nonlinear energy operator (NEO) algorithms achieves the spike detecting from action potential including complex noise. The spike detector circuit consists of a differentiator with a fully-differential structure and a multiplier based on CMOS translinear using sub-threshold technique. The differentiator has the steepness of a transmission function with frequency +20 dB/dec, frequency response from 10 Hz to 10.5 kHz. The linear range of multiplier is from −0.9 V to 0.9 V at V_DD = ±1.65 V. The spike detector is implemented in 0.35 μm technology with fully-CMOS process. One detector die size is 0.0187 mm² and its total current consumption of 825 nA. As is demonstrated by measured results, the proposed circuit has detected the instantaneous energy of the input real spike signals well, which the noise of small than 218 μV_rms over a nominal bandwidth of 500–10.5 kHz.     

Scaling down of organic complementary logic gates for compact logic on foil

In this work, we realize complementary circuits with organic p-type and n-type transistor integrated on polyethylene naphthalate (PEN) foil. We employ evaporated p-type and n-type organic semiconductors spaced side by side in bottom-contact bottom-gate coplanar structures with channel lengths of 5 μm. The area density is 0.08 mm² per complementary logic gate. Both p-type and n-type transistors show mobilities >0.1 cm²/V s with V_on close to zero volt. Small circuits like inverters and 19-stage ring oscillators (RO) are fabricated to study the static and the dynamic performance of the logic inverter gate. The circuits operate at V_dd as low as 2.5 V and the inverter stage delay at V_dd = 10 V is as low as 2 μs. Finally, an 8 bit organic complementary transponder chip with data rate up to 2.7 k bits/s is fabricated on foil by successfully integrating 358 transistors.     

IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures

Thin film transistors (TFTs) with bottom gate and staggered electrodes using atomic layer deposited Al₂O₃ as gate insulator and radio frequency sputtered In–Ga–Zn Oxide (IGZO) as channel layer are fabricated in this work. The performances of IGZO TFTs with different deposition temperature of Al₂O₃ are investigated and compared. The experiment results show that the Al₂O₃ deposition temperature play an important role in the field effect mobility, I_on/I_off ratio, sub-threshold swing and bias stability of the devices. The TFT with a 250 °C Al₂O₃ gate insulator shows the best performance; specifically, field effect mobility of 6.3 cm²/Vs, threshold voltage of 5.1 V, I_on/I_off ratio of 4×10⁷, and sub-threshold swing of 0.56 V/dec. The 250 °C Al₂O₃ insulator based device also shows a substantially smaller threshold voltage shift of 1.5 V after a 10 V gate voltage is stressed for 1 h, while the value for the 200, 300 and 350 °C Al₂O₃ insulator based devices are 2.3, 2.6, and 1.64 V, respectively.     

Oscillation-controlled CMOS ring oscillator for wireless sensor systems

This paper presents a ring oscillator with the function of the oscillation controlled for wireless sensor systems (WSSs). The proposed oscillator consists of a NAND gate, 4 inverters, and 1-, 3-, 9-times buffer stage. Operation of it is controlled by the NAND gate. The oscillator can reduce the power loss because the oscillator is oscillated during only high level input. The proposed oscillator was designed and fabricated by 2.5 μm CMOS technology, through which it is possible to realize a WSS on a single chip because a sensor and an oscillator can be fabricated concurrently.The frequency tuning range of the oscillator was found to be approximately 90–152 MHz and the output power of the oscillator was ?8.42 dBm. The measured phase noise is ?99.35 and ?102.59 dBc/Hz at 1 and 5 MHz offsets, respectively, from the carrier of 152 MHz. Power consumption of the oscillator is determined by the duty cycle of the input signal pulse, and the range of power consumption was measured as 1.5–45 mW at the duty cycle of 1.0.     

Solution-processed single-crystal perylene diimide transistors with high electron mobility

We have successfully demonstrated a single-crystal field-effect transistors (FETs) based on an asymmetric perylenetetracarboxylic diimide (a-PDI) compound with polystyrene (PS)/SiO₂ bilayer as gate dielectric. The single crystals are in-situ grown on substrate from simple solution evaporation method, thus may be suitable for large area electronics applications. The PS modified gate dielectric could minimize charge trapping by the hydroxyl groups of the SiO₂ surface. The resulting solution processed single crystals transistors are characterized in ambient air, and exhibited maximum electron mobility of ca. 1.2 cm² V⁻¹ s⁻¹ and high I_on:I_off > 10⁵.     

Impact of NBTI induced variations on delay locked loop multi-phase clock generator

Negative bias temperature instability (NBTI) is a serious reliability concern for both analog and digital CMOS VLSI circuits. The shift in threshold voltage and reduction in drain current due to NBTI in p-channel MOSFETs are time, bias and temperature dependent. The degradation of the PMOS at any critical nodes in the circuit leads to the failure of the circuit immediately or in few months/year. The Delay-Locked-Loop (DLL) which is used as multi-phase clock generator for microprocessors, frequency synthesizers, time-to-digital converter (TDC) etc. reduces the phase error between output and reference clock until it is locked. The delay variations due to process, voltage and temperature fluctuations are governed by its feedback system. At start-up, the phase shift of the output clock should lie between 0.5 and 1.5 times the time period of the reference clock to achieve regular locking. The deviations from the above criteria due to NBTI degradation directly affect the control system and lead to erroneous locking. The NBTI-induced time-dependent variation in PMOS of the delay stage in voltage-controlled delay line (VCDL) of DLL affects the delay in each stage of VCDL and propagates as phase error to the output clock. This paper analyzes the impact of NBTI-induced time-dependent variations in Delay-Locked-Loop (DLL) based clock generators for the first time. The DLL is designed with 180 nm technologies with working frequency range from 75 MHz to 220 MHz. The time dependent variations in VCDL, the most sensitive blocks of DLL, are analyzed. It is observed that these time-dependent variations increase the phase error and the working of DLL is severely affected at the rearmost end of frequency range. The output clock gets deviated and observed to be locked late after π/2 or π radians from the nominal lock. It is essential to prevent DLL locking to an incorrect delay or false lock and to bring the output clock back to the correct position. An adaptive body bias circuit is proposed in this paper to reduce the impact of NBTI degradation and thereby to prevent erroneous locking in DLL.     

Novel organic inverters with dual-gate pentacene thin-film transistor

We report on the fabrication and characterization of dual-gate pentacene organic thin-film transistors (OTFTs) with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al₂O₃ as a bottom-gate dielectric and PEALD 200 nm thick Al₂O₃ as a top-gate dielectric. The V_th of dual-gate OTFT has changed systematically with the application of voltage bias to top-gate electrode. When voltage bias from −10 V to 10 V is applied to top gate, V_th changes from 1.95 V to −9.8 V. Two novel types of the zero drive load logic inverter with dual-gate structure have been proposed and fabricated using PEALD Al₂O₃ gate dielectrics. Because the variation of V_th due to chemical degradation and the spatial variation of V_th are inherent in OTFTs, the compensation technology by dual-gate structure can be essential to OTFT applications.     

A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer

In this paper, we present a 90-nm high gain (24 dB) linearized CMOS amplifier suitable for applications requiring high degree of port isolation in the K_u-band (13.2–15.4 GHz). The two-stage design is composed of a low-noise common-gate stage and a gain-boosting cascode block with an integrated output buffer for measurement. Optimization of input stage and load-port buffer parameters improves the front-end's linear coverage, port return-loss, and overall gain without burdening its power demand and noise contribution. With low gate bias voltages (0.65–1.2 V) and an active current source, <?10 dB port reflection loss and 3.25–3.41 dB NF are achieved over the bandwidth. The input reflection loss of the overall amplifier lies between ?35 and ?10 dB and the circuit demonstrates a peak forward gain of 24 dB at 14.2 GHz. The output buffer improves the amplifier's forward gain by ～9 dB and pushes down the minimum output return loss to ?22.5 dB while raising the front-end NF by only 0.05 dB. The effect of layout parasites is considered in detail in the 90-nm process models for accurate RF analysis. Monte Carlo simulation predicts 9% and 8% variation in gain and noise figures resulting from a 10% mismatch in process. The K_u-band amplifier including the buffer block consumes 7.69 mA from a 1.2-V supply. The proposed circuit techniques achieve superior small signal gain, GHz-per-milliwatt, and range of linearity when compared with simulated results of reported microwave amplifiers.     

ZrO2 insulator modified by a thin Al2O3 film to enhance the performance of InGaZnO thin-film transistor

A high-performance InGaZnO (IGZO) thin-film transistor (TFT) with ZrO₂–Al₂O₃ bilayer gate insulator is fabricated. Compared to IGZO-TFT with ZrO₂ single gate insulator, its electrical characteristics are significantly improved, specifically, enhancement of I_on/I_off ratios by one order of magnitude, increase of the field-effect mobility (from 9.8 to 14 cm²/Vs), reduction of the subthreshold swing from 0.46 to 0.33 V/dec, the maximum density of surface states at the channel-insulator interface decreased from 4.3 × 10¹² to 2.5 × 10¹² cm⁻². The performance enhancements are attributed to the suppression of leakage current, smoother surface morphology, and suppression of charge trapping by using Al₂O₃ films to modify the high-k ZrO₂ dielectric.     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques

A CMOS analogue current-mode multiplier/divider circuit is presented. It is based on a dynamic biasing applied at the bulk terminal of MOS transistors operating in both saturation and triode. With the proposed structure, the multiplier forms a feedback loop that improves the current swing and accuracy. The multiplier has been fabricated using a standard 0.18 µm CMOS technology. The circuit consumes 144 µW using a single supply voltage of 1.8 V with a measured THD lower than 1% for an output current of 38 µA, and requires a die area of 90 µm x 45 µm.     

Phonon-scattering effects in CNT-FETs with different dimensions and dielectric materials

The impact of acoustic and optical phonon scattering on the performance of CNT-FETs is investigated using a full-quantum transport model within the NEGF formalism. Different gate lengths, dielectric materials and chiralities are considered. It is shown that the use of a high-κ dielectric lowers the off-current dominated by phonon-assisted band-to-band tunneling. The device scalability is demonstrated: with the oxide thickness fixed to 1.5 nm, good performance is obtained with 15 nm and 10 nm gate lengths with SiO₂ and HfO₂ gate dielectrics, respectively. The role of phonon scattering in CNT-FETs of different chiralities is investigated for the HfO₂ devices. A similar analysis has also been carried out for source/drain underlap geometries. The results confirm that the calculation of the off-currents and delay times is strongly influenced by phonon scattering.     

Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain

The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance g_ds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an f_T of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic f_T of 165 GHz and an extrinsic f_max of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic f_T and f_max of 120 GHz and 110 GHz, respectively.     

Sub 0.5-V bulk-driven LTA in 0.18 μm CMOS

The paper deals with a new solution for an ultra-low-voltage loser take all (LTA) circuit, capable to operate from supply voltages ranging from 0.3 to 0.5 V. The proposed circuit exploit the idea of multiple voltage buffers with a common output. In order to obtain a compact and precise LTA, a new kind of an ultra-low-voltage buffer has been developed. Owing to the fact that for such a low supply voltage the available voltage swing is highly reduced, the impact of transistor mismatches and speed-accuracy-power tradeoffs have extensively been discussed in the paper. While implemented in a standard 0.18 μm CMOS process, the proposed LTA circuit in a two-input version consumes 3.0 μW from a 0.5 V supply and provides 10 μs crossover recovery time for a 1 pF load capacitance.     

Voltage dependent degradation of HfSiON/SiO2 nMOSFETs under positive bias temperature instability

This paper investigates voltage-dependent degradation of HfSiON/SiO₂ nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime t_L = 1.64 × 10¹⁰ s, which agreed well with the t_L = 1.92 × 10¹⁰ s measured at low gate stress voltage, whereas the conventional model overestimates t_L by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating t_L of high-k nMOSFETs.     

Novel GaAs enhancement-mode/depletion-mode pHEMTs technology using high-k praseodymium oxide interlayer

In this study, a novel metal–semiconductor gate enhancement-mode (E-mode) and a metal–insulator-metal–semiconductor (MIMS) gate depletion-mode (D-mode) AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) on a single GaAs substrate have been developed by using high dielectric constant praseodymium insulator layer. The epitaxial layers were design for an enhancement-mode pHEMT after gate recess process. To achieve E/D-mode pHEMTs on single GaAs wafer, traditional Pt/Ti/Au metals were deposited as Schottky contact for E-mode pHEMTs and Pr/Pr₂O₃/Ti/Au were deposited as MIMS-gate for D-mode pHEMTs. This AlGaAs/InGaAs E-mode pHEMTs exhibit a gate turn-on voltage (V_ON) of +1 V and a gate-to-drain breakdown voltage of ?5.6 V, and these values were +7 V and ?34 V for MIMS-gate D-mode pHEMTs, respectively. Therefore, this high-k insulator in D-mode pHEMT is beneficial for suppressing the gate leakage current. Comparing to previous E/D-mode pHEMT technology, this E-mode pHEMTs and MIMS-gate D-mode pHEMTs exhibit a highly potential for high uniformity GaAs logic circuit applications due to its single recess process.