A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system forAM/FM radio receivers

ΣΔ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time ΣΔ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm² in 0.25-μm standard digital CMOS. The ΣΔ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW     

Quadrature bandpass ΔΣ modulation for digital radio

A quadrature bandpass ΔΣ modulator IC facilitates monolithic digital-radio-receiver design by allowing straightforward “complex A/D conversion” of an image reject mixer's I and Q, outputs. Quadrature bandpass ΔΣ modulators provide superior performance over pairs of real bandpass ΔΣ modulators in the conversion of complex input signals, using complex filtering embedded in ΔΣ loops to efficiently realize asymmetric noise-shaped spectra. The fourth-order prototype IC, clocked at 10 MHz, converts narrowband 3.75-MHz I and Q inputs and attains a dynamic range of 67 dB in 200-kHz (GSM) bandwidth, increasing to 71 and 77 dB in 100- and 30-kHz bandwidths, respectively. Maximum signal-to-noise plus distortion ratio (SNDR) in 200-kHz bandwidth is 62 dB. Power consumption is 130 mW at 5 V. Die size in a 0.8-μm CMOS process is 2.4×1.8 mm²      

A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digitalconversion of a 10 MHz FM signal

In many wireless applications, it is necessary to demodulate and digitize frequency or phase modulated signals. Most commonly, this is done using separate frequency discrimination and analog-to-digital (A/D) conversion. In low-cost IC technologies, such as CMOS, precise analog frequented discrimination is not practical, so the A/D conversion is usually performed in quadrature or at a nonzero intermediate frequency (IF) with digital frequency discrimination. While practical, the approach tends to require complicated A/D converters, and accuracy is usually limited by the duality of the A/D conversion. This paper presents an alternative structure, referred to as a delta-sigma frequency-to-digital converter (ΔΣFDC), that simultaneously performs frequency demodulation and digitization. The ΔΣFDC is shown to offer high-precision performance with very low analog complexity. A prototype of the key component of the ΔΣFDC has been fabricated in a 0.6 μm, single-poly, CMOS process. The prototype achieved 50 kSample/s frequency-to-digital conversion of a 10 MHz frequency-modulated signal with a worst case signal-to-noise-and-distortion ratio of 85 dB and a worst case spurious-free dynamic range of 88 dH     

A fourth-order bandpass sigma-delta modulator

The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta (ΣΔ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio     

Architecture, design, and test of continuous-time tunableintermediate-frequency bandpass delta-sigma modulators

This paper examines the architecture, design, and test of continuous-time tunable intermediate-frequency (IF) fourth-order bandpass delta-sigma (BP ΔΣ) modulators. Bandpass modulators sampling at high IFs (~100 MHz) allow direct sampling of the RF signal-reducing analog hardware and make it easier to realize completely software programmable receivers. This paper presents circuit design of and test results from continuous-time fourth-order BP ΔΣ modulators fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f_T) of 80 GHz and a maximum frequency of oscillation (f_MAX) of about 130 GHz. Operating from ±5-V power supplies, a fabricated 180-MHz IF fourth-order ΔΣ modulator sampling at 4 GS/s demonstrates stable behavior and achieves 75.8 dB of signal-to-(noise+distortion)-ratio (SNDR) over a 1-MHz bandwidth. Narrowband performance (~1 MHz) performance of these modulators is limited by thermal/device noise while broadband performance (~60 MHz), is limited by quantization noise. The high sampling frequency (4 GS/s) in this converter is dictated by broadband (60 MHz) performance requirements     

A fourth-order bandpass Δ-Σ modulator usingsecond-order bandpass noise-shaping dynamic element matching

This paper describes a multibit bandpass ΔΣ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-μm CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz     

80 MHz bandpass delta-sigma modulator using switched-capacitorresonator structure

A fully differential 80 MHz fourth-order bandpass ΔΣ modulator, meant for a 100 MHz GSM/WCDMA multimode IF receiver, is presented. The modulator is based on a double-delay single opamp SC-resonator structure which is well suited for low supply voltages. Furthermore, the centre frequency of the topology is insensitive to different component variances. The measured peak SNR is 78 dB and 43.3 dB for 270 kHz (GSM) and 3.84 MHz (WCDMA) bandwidths, respectively     

A CMOS 0.8-μm transistor-only 1.63-MHz switched-current bandpassΣΔ modulator for AM signal A/D conversion

This paper presents a CMOS 0.8-μm switched-current (SI) fourth-order bandpass ΣΔ modulator (BP-ΣΔM) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z^-1 →-z^-2) to a 1-bit second-order low-pass ΣΔ modulator (LP-ΣΔM). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz     

A 13.5-b 1.2-V micropower extended counting A/D converter

This work presents a study of the extended counting technique for a 1.2-V micropower voice-band A/D converter. This extended counting technique is a blend of ΣΔ modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. To achieve this, the converter successively operates first as a first-order ΣΔ modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. An experimental prototype was designed in 0.8-μm CMOS. With a 1.2-V power supply, it consumes 150 μW of power at a 16-kHz Nyquist sampling frequency. The measured peak S/(N+THD) was 80 dB and the dynamic range 82 dB. The converter core including the controller and all reconstruction logic occupies about 1.3×1 mm² of chip area. This is considerably less than a complete ΣΔ modulation A/D converter where the digital decimation filter would occupy a significant amount of chip area     

A 1.8-mW CMOS ΣΔ modulator with integrated mixer forA/D conversion of IF signals

In this paper, the design of a continuous-time baseband sigma-delta (ΣΔ) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF ΣΔ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF ΣΔ modulator is 0.2 mm² in 0.35-μm CMOS     

A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSMdual-standard IF reception

A system-oriented approach for the design of a UMTS/GSM dual-standard ΔΣ modulator is presented to demonstrate the feasibility of achieving intermediate frequency (IF) around 100 MHz, high dynamic range, and low power consumption at the same time. The circuit prototype implements 78 MHz IF for GSM and 138.24 MHz for wideband code division multiple access (WCDMA), which are set to be 3/4 of the analog-to-digital converter sampling rate. A two-path IF sampling and mixing topology with a low-pass ΔΣ modulator, run at half the sampling rate, is used. Implemented in 0.25-μm CMOS, the circuit achieves dynamic range and peak signal-to-noise and distortion ratio for GSM of 86 and 72 dB, respectively. The corresponding values for WCDMA are 54 and 52 dB, respectively. Optimization is performed at all stages of design to minimize power consumption. The complete circuit consumes less than 11.5 mW for GSM and 13.5 mW for WCDMA at 2.5-V supply, of which 8 mW is due to the analog part     

A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulatorwith 74-dB dynamic range

A 3.3-V bandpass ΣΔ modulator for IF sampling at 10.7 MHz in digital radio applications has been developed. The modulator presents a sixth-order single-loop architecture and features a 74-dB dynamic range in a 2OO-kHz signal bandwidth (FM signal), while for a 9-kHz signal bandwidth (AM signal) the dynamic range is 88 dB. The modulator has been integrated in a standard 0.35-μm CMOS technology using switched-capacitor technique and consumes 76 mW from a single 3.3V supply     

A two-path bandpass ΣΔ modulator for digital IFextraction at 20 MHz

Oversampled bandpass A/D converters based on sigma-delta (ΣΔ) modulation can be used to robustly digitize the types of narrowband intermediate frequency (IF) signals that arise in radios and cellular systems. This paper proposes a two-path architecture for a fourth-order, bandpass modulator that is more tolerant of analog circuit limitations at high sampling speeds than conventional implementations based on the use of switched-capacitor biquadratic filters. An experimental prototype employing the two-path topology has been integrated in a 0.6-μm, single-poly, triple-metal CMOS technology with capacitors synthesized from a stacked metal structure. Two interleaved paths clocked at 40 MHz digitize a 200-kHz bandwidth signal centered at 20 MHz with 75 dB of dynamic range while suppressing the undesired mirror image signal by 42 dB. At low input signal levels, the mixing of spurious tones at DC and f_s/2 with the input appears to degrade the performance of the modulator; out-of-band sinusoidal dither is shown to be an effective means of avoiding this degradation. The experimental modulator dissipates 72 mW from a 3.3 V supply     

A two-path bandpass sigma-delta modulator with extended noiseshaping

A three-stage bandpass sigma-delta (ΣΔ) analog-to-digital converter has been designed specifically for operation at low oversampling ratios. In the proposed architecture, the center frequency of the third stage is shifted slightly from that of the first two stages to achieve more efficient noise shaping across the signal band. An experimental modulator based on the proposed topology has been integrated in a 0.25-μm CMOS technology and achieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distortion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an f_s/4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and its active area is 4 mm²     

A 16-b 320-kHz CMOS A/D converter using two-stage third-orderΣΔ noise shaping

The design and measured performance of a two-stage third-order ΣΔ (sigma-delta) analog-to-digital (A/D) converter is described. The A/D converter achieves a 96-dB dynamic range and a maximum signal-to-noise-plus-distortion ratio (S/(N+ D)) r.m.s./r.m.s. of 93 dB with 320-kHz output rate and an oversampling ratio of 64. An analysis of the integrator gain error is presented. The modulator is realized in a 1.2-μm double-metal single-poly CMOS process with an active area of 1.6 mm². This modulator operates from a 5-V power supply and a single reference voltage     

CMOS fully-differential bandpass ΣΔ modulator usingswitched-current circuits

The authors present a fourth-order bandpass ΣΔ switched-current modulator IC in 0.8 μm CMOS single-poly technology. It is the first reported integrated circuit realisation of a bandpass ΣΔ modulator using switched-current circuits. Its architecture is obtained by applying a lowpass to bandpass transformation (z¹→-z²) to a second-order lowpass modulator. It has been realised using fully-differential circuitry with common-mode feedback. Measurements show 8 bit dynamic range up to 5 MHz clock frequency     

A CMOS delta-sigma true RMS converter

Conventionally, monolithic electronics true rms converters are constructed by bipolar circuitry. This paper describes a new architecture based on delta-sigma (ΔΣ) modulation to realize a low-cost rms converter in CMOS technologies, especially intended for handheld digital multimeters. The signal-to-quantization noise ratio as well as transfer characteristics of this architecture have been deduced to obtain initial design parameters. The use of an indirect charge transfer technique makes the converter gain depend only on an on-chip capacitor ratio, reducing gain drift and offering good gain accuracy. Measured results show that this converter achieves a signal-to-noise ratio of 88 dB and a relative error of ±0.2% for arbitrary inputs with a signal crest factor up to three. The signal bandwidth exceeds 50 kHz, and the full-scale input range is greater than 0.4 V_rms. Without trimming and calibration, this converter has an absolute gain error less than ±0.4%. This chip is fabricated in a 0.8-μm double-poly, double-metal CMOS process and occupies active area of 1 mm ²     

A CMOS analog front-end circuit for an FDM-based ADSL system

A CMOS analog front-end circuit for an FDM-based ADSL system is presented. The circuit contains all analog functions including AGC amplifiers, continuous-time band pass filters, ΣΔ AD/DA converters, and digital decimation and interpolation filters. On-chip automatic tuning of the bandpass filters provides more than 300% center frequency range with 1% frequency accuracy. The higher-order ΣΔ AD/DA converters achieve 12-b data conversion at 1.54 Msamples/s with an oversampling ratio of only 32. The 0.7 μm CMOS circuit measures 65 mm² and consumes 1.9 W from a single 5 V power supply     

A 15-b resolution 2-MHz Nyquist rate ΔΣ ADC in a1-μm CMOS technology

A high-resolution high-speed fourth-order cascaded ΔΣ analog-to-digital converter, based on a 2-1-1 topology, is presented. The converter is implemented with fully differential switched capacitor circuits in a standard 1-μm CMOS technology. The converter uses two symmetrical reference voltages of 1 V, and is driven by a single 48-MHz clock signal. With an oversampling ratio of only 24, the converter achieves a resolution of 91 dB, a peak SNR of 90 dB, and a peak SNDR of 85 dB at a Nyquist rate of 2 MHz after comb filtering. The power consumption of the converter is 230 mW, from a single 5-V supply voltage     

Influence of the feedback DAC delay on continuous-time bandpassΣΔ coverter

An analysis of the effect of the feedback digital-to-analogue converter (DAC) delay on the synthesis results of continuous-time ΣΔ bandpass modulators is presented. It is shown that non-null values of the feedback DAC delay can be optimal with respect to the filter gain margin