一种用于模式识别的新型多功能开关电流模糊处理器

本文首次提出了一种用于模式识别的新型多功能开关电流模糊处理器．该模糊处理器不仅可以求出最大综合隶属度相应的标准模式，而且可以按综合隶属度大小的顺序依次输出综合隶属度以及相应的标准模式，这将十分有利于系统性能的改善．该处理器可以进行绝对拒识和相对拒识的判断，大大提高了系统的可靠性．另外，为了提高该处理器的自适应能力，将综合函数中的权重设计为可调节的．ＰＳＰＩＣＥ模拟结果表明该处理器具有高精度、高分辨率等特点．在电路上，该处理器结构简单、灵活，模块化的设计使处理器的规模易于扩展．同开关电容技术相比，开关电流技     

一种新的可编程、可扩展的Hamming神经网络

提出了一种新的可编程、可扩展Ｈａｍｍｉｎｇ神经网络．它采用电流镜计算待识模式与标准模式的匹配度．然后,通过电流型排序电路进行匹配度的排序操作并输出识别结果．该Ｈａｍ－ｍｉｎｇ神经网络中的标准模式模板是可编程的,以满足不同场合的应用要求．另外,该网络芯片在规模上可以很容易地进行扩展,这较大地提高了该处理芯片应用的灵活性．由于网络电路中模拟部分完全采用电流型电路,使其可完全直接采用标准数字ＣＭＯＳ工艺进行制作,并易于模／数混合集成．已经采用单层金属、单层多晶的２μｍＮ阱标准数字ＣＭＯＳ工艺成功地制作了该Ｈａｍ     

一种新的可编程、可扩展的Hamming神经网络

提出了一种新的可编程、可扩展Hamming神经网络。它采用电流镜计算待识模式与标准模式的匹配度。然后,通过电流型排序电路进行匹配度的排序操作并输出识别结果。该Hamming神经网络中的标准模式模板是可编程的,以满足不同场合的应用要求。另外,该网络芯片在规模上可以很容易地进行扩展,这较大地提高了该处理芯片应用的灵活性。由于网络电路中模拟部分完全采用电流型电路,使其可完全直接采用标准数字CMOS工艺进行制作,并易于模/数混合集成。已经采用单层金属、单层多晶的2pm N阱标准数字CMOS工艺成功地制作了该Hamming网络中的核心单元电路芯片,测试结果表明,该核心单元电路芯片的性能很好,完全可以满足处理器的性能要求。     

混沌光学系统的神经网络自适应控制研究

提出一种用于混沌光学系统控制的神经网络自适应控制技术。以一前向神经网络作为受控混沌光学系统的系统辩识器，由此神经网络系统辩识器与受控混沌光学系统输出差值作为负反馈对受控混沌光学系统控制参数进行调整达到控制目的。由于所使用神经网络系统辩识器在常规ＢＰ算法的支持下可从受控混沌光学系统的输出时间序列进行动力学模型重构，因而特别适用于对未知动力学表述的混沌光学系统进行控制。以对布喇格声光双稳混沌系统的系统辩识及自适应控制为例，对此神经网络自适应控制技术可行性进行了示例证明。     

一种新的高性能开关电流排序电路

本文首次提出了一种高性能的开关电流型排序电路．它采用开关电流镜跟踪／保持输入信号，通过全对称的ＷＴＡ（Ｗｉｎｎｅｒ－Ｔａｋｅ－Ａｌ）电路网络求最大，最后分时输出排序结果．该电路结构简单、灵活，规模易扩展．ＰＳＰＩＣＥ模拟结果表明，该电路的输出电流相对于输入电流的偏差小，最大偏差为５μＡ；排序电路有较高的分辨精度，在５μＡ以内．由于采用开关电流技术，该电路完全同数字ＣＭＯＳ工艺相兼容，易于ＶＬＳＩ实现     

一种新的高性能开关电容排序电路

本文首次提出了一种高性能的开关电流型排序电路．它采用开关电流镜跟踪／保持输入信号，通过全对称的ＷＴＡ（Ｗｉｎｎｅｒ－Ｔａｋｅ－Ａｌ）电路网络求最大，最后分时输出排序结果．该电路结构简单、灵活，规模易扩展．ＰＳＰＩＣＥ模拟结果表明，该电路的输出电流相对于输入电流的偏差小，最大偏差为５μＡ；排序电路有较高的分辨精度，在５μＡ以内．由于采用开关电流技术，该电路完全同数字ＣＭＯＳ工艺相兼容，易于ＶＬＳＩ实现     

双向联想记忆神经网络的开关电流技术实现

本文研究了双向联想记忆（ＢＡＭ）神经网络的开关电流技术实现，提出了实现负权值及存储联想矢量的两个开关电流单元电路，基于此，给出了双向联想记忆网络的开关电流电路，文中对三神经元双向联想记忆ＳＩ网络进行了ＰＳＰＩＣＥ仿真，结果表明所提出的ＳＩ联想记忆网络是正确的。     

一种基于神经网络跟踪控制的稳定性分析

本文针对一种标准形式的未知非线性系统的输出跟踪控制构造了一种基于多层前馈神经网络的的非线性学习控制系统，并利用ＢＰ学习算法训练好的神经网络构造了一个自适应输出跟踪控制结构。     

一种投票权值调整的神经网络集成增量学习方法

针对神经网络集成增量学习中集成输出投票权值的设定问题,给出了一种投票权值调整的神经网络集成增量学习方法。该方法定义了神经网络集成中子神经网络训练集的类核函数,通过计算待识样本与类核函数之间的核函数距离得到集成输出中子神经网络的投票权值。这种投票权值设定方法可以根据子神经网络分类器对待识样本的分类性能自适应地调整集成输出的投票权值,是一种更加合理的集成输出投票权值设定方法。仿真实验表明,这种投票权值调整的神经网络集成增量学习方法比投票权值固定的方法增量学习性能更优。      

一种快速多层神经网络训练算法及其在系统辩识中的应用

本文提出了一种新的多层前馈神经网络快速训练方法.该算法是基于指数加权局部最小二乘(EWLLS)目标函数及殴几里得方向集(EDS)方法的,在训练过程中,通过估计局部期望输出,多层神经网络可以被分解成若干个自适应线性神经元(Adaline),而Adaline是通过EDS方法进行训练的.该算法的性能是通过将其应用于系统辩识中加以说明的.     

New current-mode wave-pipelined architectures for high-speed analog-to-digital converters

In this paper, two new architectures for high-speed CMOS wave-pipelined current-mode A/D converters (WP-IADCs) are proposed and analyzed. In the new WP-IADC architectures, the wave-pipelined theory is applied to both pipeline structures, called full WP-IADC (FWP-IADC) and indirect transfer WP-IADC (ITWP-IADC). In the FWP-IADC, each stage uses the full current-mode wave-pipelined structure without switched-current cell circuits. In the ITWP-IADC, the switched-current cells are incorporated into the wave-pipelined stages which are divided into several sections with controlled clocks. Therefore, the proposed ITWP-IADC performs optimally in terms of speed and accuracy in the WP-IADCs. Generally, the proposed WP-IADCs have the advantages of high speed, high input frequency, high efficiency of timing usage, high clock-period flexibility in switched-current cells for precision enhancement, and reduced number of switched-current cells in the overall data path for linearity improvement. According to the theoretical analysis on the proposed WP-IADC structures, the minimum sampling clock period is proportional to the intrinsic delay of the current mirror and the increased rise/fall time in each wave-pipelined stage. The HSPICE simulation results reveal that, under Nyquist rate sampling in 8-b resolution, a sampling rate of 20 and 54 MHz can be achieved for FWP-IADC and two-section ITWP-IADC, respectively. If four wave-pipelined sections are used, the ITWP-IADC can be operated at 166 MHz at an input frequency of 8 MHz. To experimentally verify the correct function of the proposed WP-IADC structures, the proposed new architecture of the FWP-IADC is implemented by using 0.35-/spl mu/m CMOS technology. The measurement results successfully demonstrate the feasibility of wave-pipelined IADC architectures in applications of high-speed ADCs.     

Q-based design method for impedance matching network considering load variation and frequency drift

The key step in Q-based design for T or Pi network impedance matching is selecting an appropriate Q-factor. The harmonic rejection performance of impedance matching networks is the main concern of Q selection. However, for applications wherein the impedance to be matched is variable or the frequency is drifty, it is not the harmonic rejection but the stability, which is the main performance consideration. This paper analyzes T network impedance matching. The relationship between reflection coefficient, load variation, and frequency drift is determined, which provides a reference for Q selection. The Q-based design process presented in this paper can strike a balance between stability and harmonic rejection, which can then be applied in other cases involving load variation or frequency drift.     

Q-based design method for T network impedance matching

Impedance matching using passive network is very important in the design of RF and microwave circuits to achieve maximum power transfer, minimum reflection, and adequate harmonic rejection. This paper investigates the T network impedance matching analytically. A practical guide is provided for systematic network design based on the desired harmonic rejection specification. Expressions of the frequency response and harmonic rejection in term of the loaded Q are established. The limits of the network are analytically demonstrated. It is shown that the third harmonic rejection is about 12 dB higher than second harmonic rejection provided that the loaded Q is larger than twice the minimum Q.     

一种新型可扩展的电流排序电路

本文提出了一种新的可扩展电流型排序电路。该电路在功能上,不权可以将输入电路按大小顺序输出,而且还可以确定输出电流相应的输入端。该电路的埯序时间和面积复杂度仅为Ｏ（Ｎ）,Ｎ为待排序电流输入端数。在结构上,该电路简单、灵活,芯片之间可以扩展。由于该电路完全同数字ＣＭＯＳ工艺相兼容,易于赵大规模集成电路制作。     

An Evolutionary Method for Synthesizing Low-Sensitivity Lossless Matching Networks

Whereas the present practice of designing matching networks for antennas is limited to conventional topologies, requiring a significant amount of domain knowledge, evolutionary algorithms can be used for automatically identifying unconventional designs that are more effective than would otherwise be developed. In this work, an automatic method to design lossless matching networks driven by an evolutionary algorithm (EA) that considers the sensitivities of the network parameters during the synthesis process is presented. To this end, a closed-form expression for the transducer power gain (TPG) sensitivity with respect to the component values is employed in such a way that the effects of the components tolerance on the matching network performance can easily be quantified. A 3D data structure based on the adjacency matrix is conveniently used to represent any type of network topologies. The proposed EA employs a novel set of topology variation operators, tailored for changing the circuit topology, and an association step, with the aim of reducing the number of nodes of the matching circuit. The efficiency of the proposed EA is tested in the synthesis of an impedance matching network for a VHF monopole whip antenna. This study’s results indicate a matching bandwidth improvement, a more uniformly distributed TPG along the operation frequency band and a more stable TPG regarding the components tolerance compared to the results obtained by previous approaches.     

新型超宽带带通滤波器

提出了一种新型的短接环形多模谐振器,适合于构成超宽带带通滤波器。利用该多模谐振器的前三个谐振模式构成滤波器的整个通带．并提出通过改变多模谐振器阻抗比来控制该带通滤波器的相对带宽的方法。该结构具有易于级联的特性。通过级联可明显改善阻带特性。给出了一个单元以及三个单元级联后的滤波器结构以及通过仿真和实验获得的性能参数,验证了所设计的新型超宽带带通滤波器的有效性。     

A Low-Voltage and Low-Power Adaptive Switched-Current Sigma–Delta ADC for Bio-Acquisition Microsystems

An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a switched-current sigma-delta modulator (SISDM) and a digital decimator. In order to achieve the low-voltage requirement, a novel class-AB switched-current memory cell is adopted to implement the SISDM with the oversampling ratio (OSR) of 64. In addition, a proposed differential current comparator and a low-voltage 1-bit switched-current digit-to-analog converter (SIDAC) are used for the design of the SDM. Benefits from the SISDM using the class-AB memory cell are low power consumption and high dynamic range. Moreover, a new single-multiplier structure is presented to implement the finite-impulse-response (FIR) digital filters which are the major hardware elements in the decimator. For the various applications with different biosignal frequencies, the SDADC could be manipulated in different operating modes. The overall ADC has been implemented in a TSMC 0.18-mum 1P6M standard CMOS process technology. Without a voltage booster to raise the gate voltage of switches, measurement results show that the SISDM has a dynamic range over 60 dB and a power consumption of 180 muW with an input signal of 1.25-kHz sinusoid wave and 5-kHz bandwidth under a single 0.8-V power supply for electroneurography signals. In addition, the postlayout simulations of SDADC including SISDM and decimator reveal that the dynamic range is still over 60 dB without degrading by digital circuits     

On Dynamic Optimization of Packet Matching in High-Speed Firewalls

Packet matching plays a critical role in the performance of many network devices and a tremendous amount of research has already been invested to come up with better optimized packet filters. However, most of the related works use deterministic techniques and do not exploit the traffic characteristics in their optimization schemes. In addition, most packet classifiers give no specific consideration for optimizing packet rejection, which is important for many filtering devices like firewalls. Our contribution in this paper is twofold. First, we present a novel algorithm for maximizing early rejection of unwanted flows with minimal impact on other flows. Second, we present a new packet filtering dynamic optimization technique that uses statistical search trees to utilize traffic characteristics and minimize the average packet matching time. The proposed techniques timely adapt to changes in the traffic conditions by performing simple calculations for optimizing the search data structure. Our techniques are practically attractive because they exhibit simple-to-implement and easy-to-deploy algorithms. Our extensive evaluation study using Internet traces shows that the proposed techniques can significantly minimize the packet filtering time with reasonable memory space requirements.     

A 3 V Wideband CMOS Switched-Current A/D-Converter Suitable for Time-Interleaved Operation

The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f _in = 1.83, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 m CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.     

连续小波变换开关电流电路的实现

提出了一种用开关电流电路实现连续小波变换的方法,将连续小波变换转化为用带通滤波器组对信号进行处理,并用开关电流电路实现该带通滤波器组.文章采用基于第二代开关电流技术的带通滤波器组实现了8通道的Marr小波.仿真结果表明该滤波器组具有恒Q值,且每个带通滤波器的中心频率与理论值大致相符,从而证实了该方法的可行性.