Hot-Carrier- and Constant-Voltage-Stress-Induced Low-Frequency Noise in Nitrided High- $k$ Dielectric MOSFETs

Understanding and minimization of low-frequency noise (LFN) originating from high- $k$ (HK) gate dielectrics in newgeneration MOSFETs are of critical importance to applications in RF, analog, and digital circuits. To understand the effect of stress conditions on noise, nMOSFETs were subjected to accelerated hot-carrier stress (HCS) and positive constant-voltage stress (CVS). The additional LFN introduced through stressing was evaluated on nMOSFETs with TiN metal gate and HfSiON gate dielectric. Nitridation of HfSiO gate-dielectric MOSFETs was achieved by either a high-temperature $hbox{NH}_{3}$ anneal or a lower temperature plasma anneal. Influence of different dielectric nitridation procedures on the stress-induced degradation of transconductance, threshold properties, and LFN was studied. Worst degradation conditions, i.e., $V_{g} = V_{d}$, were used for HCS, whereas for CVS, the vertical field was fixed at 10 MV/cm for all transistors to achieve comparable stressing conditions. Plasma-nitrided devices showed less increase in their noise in the linear operation region than the thermally nitrided devices. This difference in noise behavior is attributed to the nitrogen profile across the HK/Si interface and in the bulk of the HK oxide caused by different nitridation techniques. The dielectric defect profile resultant from different annealing techniques was consistent with the spectral form of the observed drain-voltage LFN.      

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.     

Dielectric-breakdown-induced epitaxy: a universal breakdown defect in ultrathin gate dielectrics

The breakdown phenomena in SiO/sub x/N/sub y/ (EOT=20 /spl Aring/) gate dielectric under a two- stage constant voltage stress in inversion mode are physically analyzed with the aid of transmission electron microscopy. The results show that dielectric-breakdown-induced epitaxy (DBIE) remains as one of the major failure defects responsible for gate dielectric breakdown evolution even for a stress voltage as low as 2.5 V. Based on the results, the same failure mechanism i.e., presence of DBIE would be responsible for the degradation in ultrathin gate dielectrics for gate voltage below 2.5 V. It is believed that DBIE will be present in MOSFETs failed at nominal operating voltage.     

The Impact of Strain Technology on FUSI Gate SOI CMOSFET

In this paper, the impact of strain engineering on device performance and reliability for fully silicide gate silicon-on-insulator CMOSFET was investigated. With characterizing device's electrical property after hot carrier (HC) and positive/negative bias instability voltage stressing, we found similar enhancement on device performance but different behavior on voltage-stressing-induced device degradation for n/pMOSFETs. Related noise analysis and charge pumping techniques were used to investigate the strain-induced oxide defect which will accelerate device degradation after long-time HC voltage stressing and/or bias instability voltage stressing.      

基于体效应的SiC MOSFET器件栅极老化监测方法研究

长期以来,栅极老化一直是SiC MOSFET器件可靠性研究的关键,而偏置温度不稳定性则是栅极老化的重要现象。由于栅极老化的偏置温度不稳定性存在应力撤出后的恢复现象,如能在可靠性实验中快速、准确地监测SiC MOSFET器件的栅极老化变化量,对可靠性研究具有重要意义。因此,文中提出一种新的栅极老化监测方法。该方法以体效应下的阈值电压VTH(body)为基础,建立理论模型来描述VTH(body)和栅极老化之间的关系。提出在栅极电压开关过程中从体二极管电压–栅极电压曲线中得到VTH(body)的方法,并详细研究实验参数对VTH(body)的影响。此外,通过高温栅偏实验对VTH(body)的实用价值进行验证,并与栅极老化参数阈值电压VTH进行对比。实验结果证明,提出的新型栅极老化监测方法可以实现栅极老化的快速、准确及非恒温环境监测。     

A new parallel ZVS converter with less power switches and low current stress components

A new direct current (DC)/DC converter with parallel circuits is presented for medium voltage and power applications. There are five pulse‐width modulation circuits in the proposed converter to reduce current stress at low voltage side for high output current applications. These five circuits share the same power switches in order to reduce switch counts. To reduce the converter size, conduction loss, and voltage stress of power semiconductors, the series connections of power metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with high switching frequency instead of insulated gate bipolar transistor (IGBT) with low switching frequency are adopted. Thus, the voltage stress of MOSFETs is clamped at half of input voltage. The switched capacitor circuit is adopted to balance input split capacitor voltages. Asymmetric pulse‐width modulation scheme is adopted to generate the necessary switching signals of MOSFETs and regulate output voltage. Based on the resonant behavior at the transition interval of power switches, all MOSFETs are turned on under zero voltage switching from 50% load to 100% load. The circuit configuration, operation principle, converter performance, and design example are discussed in detail. Finally, experimental verifications with a 1.92 kW prototype are provided to verify the performance of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.     

高压大功率器件用高温栅偏测试装置研制

为准确评估硅IGBT和碳化硅MOSFET等高压大功率器件不同电应力及热应力条件下的栅极可靠性,研制了实时测量皮安级栅极漏电流的高温栅偏（high temperature gate bias,HTGB）测试装置。此外,该测试装置具备阈值电压在线监测功能,可以更好地监测被测器件的状态以进行可靠性评估和失效分析。为初步验证测试装置的各项功能和可靠性,运用该测试装置对商用IGBT器件在相同温度应力不同电应力条件下进行分组测试。初步测试结果表明老化初期漏电流逐渐降低,最终漏电流大小与电压应力有良好的正相关性,栅偏电压越大,漏电流越大。该测试装置实现了碳化硅MOSFET器件和硅IGBT器件对高温栅偏的测试需求且适用于各种类型的封装。     

Special reliability features for Hf-based high-/spl kappa/ gate dielectrics

Several special reliability features for Hf-based high-/spl kappa/ gate dielectrics are highlighted, including: 1) trapping-induced threshold voltage (V/sub th/) shift is much more of a concern than TDDB in determining the operating lifetime; 2) n-channel MOSFETs (nMOSFETs) are more vulnerable than p-channel MOSFETs (pMOSFETs); and 3) MOSFETs with polySi gates are more vulnerable than those with metal gates. These will be discussed in the context of existing electron/hole traps and trap generation by high-field stress. A novel technique to probe traps in ultrathin gate dielectrics, inelastic electron tunneling spectroscopy (IETS), will be shown to be capable of revealing the energies and locations of traps in high-/spl kappa/ gate dielectrics.     

Impulse partial discharge characteristics and their mechanisms under non-uniform electric field in N/sub 2//SF/sub 6/ gas mixtures

We have investigated impulse partial discharge (PD) and breakdown (BD) characteristics of a needle-plane gap in N/sub 2//SF/sub 6/ gas mixtures under positive lightning impulse voltage application, and discussed their physical mechanisms. The 50% probability PD inception voltage (PDIV/sub 50/), leader discharge onset voltage (LOV) and BD voltage (BDV/sub 50/) were measured and analyzed as a function of gas pressure and SF/sub 6/ content. Experimental results revealed the stepwise propagation process of the impulse PD and enabled us to classify the impulse PD in N/sub 2//SF/sub 6/ gas mixtures into two types, the streamer discharge and the leader discharge. We also discussed the impulse PD propagation mechanisms in terms of PD parameters such as propagation length, time interval and current pulse magnitude, and suggested a sequential relationship in the PD propagation process under non-uniform electric field.     

Intentionally inserted oxygen depleted (Ba/sub 0.5/Sr/sub 0.5/)TiO/sub 3/ layers as a model of DC-electrical degradation

The relative dielectric constant versus voltage (/spl epsiv//sub r/-V) characteristics and the current density versus electric field (J-E) characteristics of (Ba/sub 0.5/Sr/sub 0.5/)TiO/sub 3/ films, which have intentionally inserted oxygen depleted layers near the bottom electrodes, were investigated as a model of dc-electrical degradation phenomena. Our investigation demonstrated that the intentionally inserted oxygen depleted layer is the cause of the tunneling conduction.     

Impact of high-/spl kappa/ dielectric HfO/sub 2/ on the mobility and device performance of sub-100-nm nMOSFETs

Scaling of Si MOSFETs beyond the 90-nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilizing strained Si (SSi) channels. Additionally, high-/spl kappa/ dielectrics are expected to replace SiO/sub 2/ around or after the 45-nm node to reduce the gate leakage current problem, facilitating further scaling. However, aside from the many technological issues such as trapped charge and partial crystallization of the dielectric, both of which are major issues limiting the reliability and device performance of devices employing high-/spl kappa/ gate stacks, a fundamental drawback of MOSFETs with high-/spl kappa/ dielectrics is the mobility degradation due to strong soft optical phonon scattering. In this work we study the impact of soft optical phonon scattering on the mobility and device performance of conventional and strained Si n-MOSFETs with high-/spl kappa/ dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 25-nm. Additionally we have also briefly investigated the effect (the percentage change) that a trapped charge within the gate oxide will have on the drive current for both a SiO/sub 2/ oxide and an equivalent oxide thickness of high-/spl kappa/ dielectric.     

Implementation of a Soft Switching Converter with High Input Voltage

This paper presents an interleaved zero voltage switching (ZVS) DC/DC converter with high input voltage applications. In order to reduce the voltage stress of MOSFETs, two half‐bridge zeta converters are connected in series at high voltage side. Thus, the voltage stress of MOSFETs can be clamped at one‐half of input voltage. Asymmetric pulse‐width modulation (APWM) is adopted to control power switches. With the resonant behavior by the leakage inductance of transformer and the output capacitance of MOSFET at the transition interval, MOSFETs can be turned on at ZVS. For each half‐bridge zeta converter, two series transformers are connected in series at the primary side and in parallel at the secondary side in order to reduce the current stress of secondary windings for high load current applications. Interleaved PWM scheme is used to control two half‐bridge converters in order to reduce the size of output filter inductor and capacitor due to the partial ripple current cancellation. Experimental results, taken from a laboratory prototype rated at 1 kW, are presented to demonstrate the converter performance. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis and implementation of a soft switching DC/DC converter with three asymmetric PWM circuits

This paper presents a soft switching converter with three buck‐type active clamp circuits (or asymmetric half‐bridge circuits) to achieve the functions of the low power rating on the transformers and power semiconductors and low current rating on the rectifier diodes and output inductors. Three half‐bridge circuits are stacked at the high voltage side to reduce the voltage stress of each power switch at one‐half of input voltage and connected in parallel at the low voltage side to share load current and reduce the current rating on each magnetic component and the rectifier diode. Thus, the size of the output chokes is reduced. In each half‐bridge converter, the asymmetric pulse‐width modulation is adopted to control power switches. Power MOSFETs can be turned on with zero voltage during the transition interval due to the resonant behavior by the output capacitance of MOSFETs and the leakage inductance (or external inductance) of transformers. Experiments based on a laboratory prototype with 1 kW rated power are provided to demonstrate the performance of proposed converter. Copyright © 2012 John Wiley & Sons, Ltd.     

Fundamental insulation characteristic of high-pressure CO/sub 2/ gas under actual equipment conditions

SF₆ gas has been widely used in electrical power equipment such as circuit breakers and transformers due to its superior insulation and interruption characteristics. However since 1997, SF₆ gas has been designated a greenhouse gas subject to emission restrictions at COP3 (The 3rd session of the Conference Of the Parties to the United Nations Framework Convention on Climate Change) so a new insulating gas is needed as a substitute for SF₆ gas. This research considers the use of high-pressure CO₂ gas as an insulator while stressing the environment aspects. Fundamental insulation data for the insulating gas acquired supposing gas insulated switchgears (GIS) consists of; (1) insulation breakdown characteristics under clean conditions and, (2) insulation breakdown characteristics with metallic particle contamination. The parameters in this case were assumed from an actual apparatus viewpoint, to be a high gas pressure up to 2.0 MPa, an electrode size capable of determining the surface area effect, the electrode surface roughness, and metallic particle length, etc. at the base electrode of the 72 kV GIS. As a result, experiments using these parameters revealed insulation characteristics for high-pressure CO₂ gas and that negative lightning impulse decided the insulation design, as well as the present SF₆ GIS. The need for taking measures to suppress PD under AC voltage and also the need for restricting metallic foreign particles around the central conductor and insulating spacer were recognized     

Widely tunable Al/sub 2/O/sub 3/-GaAs DBR filters with variable tuning characteristics

We demonstrate an optical tunable filter using Al/sub 2/O/sub 3/-GaAs layers as the top distributed Bragg reflector mirror. The mechanical properties and spectral response versus voltage are characterized. The tuning characteristics can be changed by removing the tensile-stressed Si/sub 3/N/sub 4/ on the mirror and legs. An integrated optical-mechanical model is used to analyze the result. Axial nitride and initial residual stress are incorporated into the model to obtain accurate fit. A 64-nm tuning range with 12-V tuning voltage is measured, a significant improvement over previous designs.     

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.     

A study on the competition between bias-induced charge trapping and light-induced instability in In-Ga-Zn-O thin-film transistors

Thin-film transistors (TFTs) were fabricated using In-Ga-Zn-O (IGZO) semiconductor layers deposited under different oxygen partial pressures. The devices were subjected to negative bias stress (NBS), negative bias illumination stress (NBIS), positive bias stress (PBS) and positive bias illumination stress (PBIS). While device degradation is negligible under NBS, negative shifts in the threshold voltage (V_th) are observed in the presence of light (NBIS), of which the magnitude (ΔV_th) decreases with increasing oxygen partial pressure during IGZO growth. Under PBS, the devices undergo positive V_th shifts, which become more severe with increasing oxygen content in IGZO. However, negative ΔV_th values are observed under PBIS, of which the magnitude decreases with increasing oxygen content in the semiconductor. When positive gate bias is applied, the trapping of negative charge by interstitial oxygen atoms in IGZO is presumed to be the driving force inducing positive V_th shifts. On the other hand, when light is present, the generation of photo-induced excess carriers from oxygen-deficient defect sites is anticipated to be the driving force inducing negative V_th shifts. A balance between the competing mechanisms inducing either positive or negative V_th shifts must therefore be established when the devices are subjected to PBIS, for example in operating active matrix organic light emitting diode (AMOLED) displays using transparent panel arrays.     

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better V/sub th/-L roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain (g/sub m/R/sub o/) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.     

Power frequency dependence of space charge behavior and partial discharge characteristics in SF/sub 6/ gas

The partial discharge (PD) and breakdown (BD) characteristics in SF/sub 6/ gas under commercial and higher frequency (/spl sim/600 Hz) ac voltage applications were investigated using high-speed electrical and optical measuring techniques with phase gate control method. Experimental results revealed that 400 Hz BD voltage at a certain gas pressure range was higher than that for 60 Hz and PD characteristics especially at the positive PD inception phase were much influenced by the applied power frequency. From these results, we clarified the dependence of space charge behavior on the applied power frequency and discussed the physical mechanism of PD and BD in SF/sub 6/ gas with consideration of the space charge behavior generated by PD in the previous half cycle of ac voltage.     

Electrostatic discharge effects in ultrathin gate oxide MOSFETs

The effects of destructive and nondestructive electrostatic discharge (ESD) events applied either to the gate or drain terminal of MOSFETs with ultrathin gate oxide, emulating the occurrence of an ESD event at the input or output IC pins, respectively, were investigated. The authors studied how ESD may affect MOSFET reliability in terms of time-to-breakdown (TTBD) of the gate oxide and degradation of the transistor electrical characteristics under subsequent electrical stresses. The main results of this paper demonstrate that ESD stresses may modify the MOSFET current driving capability immediately after stress and during subsequent accelerated stresses but do not affect the TTBD distributions. The damage introduced by ESD in MOSFETs increases when the gate oxide thickness is reduced.