Design of a Compact Ka-band Balanced Mixer Based on a Novel Wide-band Equivalent Circuit of the Schottky Diode

A compact Ka-band balanced mixer based on a novel Schottky diode model is presented in this paper. According to its physical structure, a novel 3D electromagnetic model of the Schottky diode is proposed. Meanwhile, a wide-band equivalent circuit is built, which takes all high frequency effects existing in the diode into account. All the parasitic reactances are extracted from the electromagnetic model-based S-parameters up to 110 GHz. Based on the proposed equivalent circuit, a Ka-band balanced mixer is designed and optimized, where bandpass filters with open stubs and a lowpass filter based on defected ground structure cells are used. The measured results show that the conversion loss is below 9 dB from 30 GHz to 40 GHz with the minimum of 6.7 dB at 35 GHz. The normalized size of the mixer is only 3.3λ _g  × 3.3λ _g , whereλ _g is the wavelength at 35 GHz.     

Design of Composite Right/Left-Handed Coplanar-Waveguide Bandpass and Dual-Passband Filters

The design and implementation of novel coplanar-waveguide (CPW) bandpass and dual-passband filters that consist of the composite right/left-handed short-circuited stubs are proposed. In contrast to the conventional short-circuited stub, whose input impedance repeats every half-wavelength, the composite right/left-handed CPW stub combines the phase-lead composite right/left-handed CPW and the phase-lag uniform CPW to achieve the arbitrary resonant frequencies with compact size. The equivalent bandpass and dual-passband LC resonators are established by investigating the frequency responses of the composite right/left-handed CPW stubs. The composite right/left-handed CPW bandpass filter is 62.5% more compact than the conventional quarter-wavelength shunt-stub CPW bandpass filter. The composite right/left-handed CPW dual-passband filter, which possesses the sharp rejection between the two asymmetric passbands, is also developed. The synthesis procedures of the composite right/left-handed CPW bandpass and dual-passband filters are successfully validated by measurement and full-wave simulation.     

Tunable Coplanar Waveguide Phase Shifter Using Ba<Subscript>x</Subscript>Sr<Subscript>1−x</Subscript>TiO<Subscript>3</Subscript> Thin Films on LaAlO<Subscript>3</Subscript> Substrates

A kind of distributed coplanar waveguide (CPW) phase shifter based on LaAlO₃ substrates is designed and fabricated in this paper. The Ba_0.4Sr_0.6TiO₃ (BST) thin films employed in the circuits are deposited by RF magnetron sputtering, and then annealed at 800°C for 30 min in air. The dielectric tunability, loss tangent of the BST films are respectively 43.7% and 0.017 at 100 kHz and 30 V, the leakage current is approximately 1 × 10⁻⁹A/cm² at zero bias voltage. The CPW phase-shifter designed is subsequently fabricated in order to obtain a 360° phase shift at 30 GHz with a moderate bias voltage. The maximal phase shift is 372° at 22.5 GHz with a bias voltage of 40 V.     

Dual band notched UWB-BPF based on hybrid microstrip-to-CPW transition

The research paper proposes a compact dual notched band ultra-wideband (UWB) bandpass filter (BPF). The basic architecture of the filter is developed using the hybrid microstrip-to-coplanar waveguide (CPW) technology, wherein a short circuited CPW in ground is coupled vertically via the dielectric to the microstrip lines on the top plane. The broadside alignment generates a three pole BPF with dual transmission zeros (TZs) on either passband/stopband edges which leads to minimum insertion loss passband and sharp roll-offs. Later, multiple spirals and split ring resonators (SRRs) are embedded in the CPW of the UWB filter to introduce the dual notches and widen the stopband respectively. The proposed filter is fabricated to justify its measured response. The proposed filter measures only 14.6 × 7.3 mm².     

A compact planar ultra-wideband bandpass filter with multiple resonant and defected ground structure

A compact bandpass filter with dumbbell shape Defected Ground Structure (DGS) operating on ultra wide pass band (UWB – 3.1 to 10.6 GHz) is proposed. It is based on hybrid microstrip coplanar waveguide (dual sided metal) structure. A Multiple Resonant Structure (MRS) is constructed using coplanar waveguide (CPW) planar transmission line. The MRS makes the resonance using quarter wavelength and half wavelength open-ended CPW. The equispaced three resonances at lower (3.1 GHz), center (6.85 GHz) and higher edge (10.6 GHz) of the whole Ultra Wide Band is achieved using CPW MRS. To make the band as flat as possible, two more resonances are introduced using quarter wavelength microstrip patches on top of the commonly shared substrate, so the proposed filter becomes a five pole bandpass filter. A dumbbell shaped defected ground structure on either side of CPW MRS improves the return loss almost less than 20 dB over the whole UWB passband. The simulated results of proposed filter show good transmission response within passband and good rejection in out of the band. The simulated and measured results are very close to each other which proves the efficacy of proposed design.     

Modeling of symmetric composite right/left-handed coplanar waveguides with applications to compact bandpass filters

This study proposes an equivalent-circuit model for the composite right/left-handed (CRLH) coplanar waveguide (CPW) comprising the series interdigital capacitor and shunt meandering short-circuited stub inductor in symmetric configuration. The new technique for extracting the equivalent-circuit elements of the CRLH CPW, which include inductances, capacitances, and resistances to represent the left-handed, right-handed, and lossy characteristics, is developed based on the effective medium concept. The applications to the compact resonators and filters are presented to emphasize the unique features of the CRLH CPW. A novel CRLH CPW resonator with a 0/spl deg/ effective electrical length at resonance is proposed, which gives a 49.1% size reduction when compared with the conventional half-wavelength resonator at 5 GHz. Based on the zeroth-order CRLH CPW resonators, an inductively coupled two-pole bandpass filter with 5.4% 3-dB bandwidth and 2.7-dB insertion loss at 5 GHz is implemented, and it is 51.4% more compact than the conventional structure. A good agreement among the results of the full-wave simulation, equivalent-circuit model, published data, and measurement demonstrates the effectiveness of the proposed modeling technique. To suppress the higher order harmonic spurious passbands, the electromagnetic-bandgap CPW structures are incorporated into the proposed CRLH CPW filter.     

Compact Millimeter-wave filters using distributed capacitively loaded CPW resonators

In this paper, a method for reducing the size of coplanar-waveguide (CPW) resonators, used in the design of compact bandpass filters, is presented. This is accomplished by incorporating a distributed array of capacitive loads along a resonant CPW line. Design of a miniaturized bandpass filter using capacitively loaded CPW resonators, which are inductively coupled, is presented. Inductively coupled bandpass filters with the proposed capacitively loaded CPW line resonators are designed and a size reduction of 25%, compared with filters using a standard CPW line resonator, is demonstrated. It is shown that, through this size reduction, the insertion loss is minimally increased (<0.4 dB). A hybrid algorithm, combining the method of moments (MOM) and circuit simulation is used to facilitate design process. Few filters using this technique are designed, fabricated, and measured at W-band. An excellent agreement between the simulation and measurement responses of these filters is presented.     

A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC

In H.264/AVC, the concept of adapting the transform size to the block size of motion-compensated prediction residue has proven to be an important coding tool. This paper presents highly parallel joint circuit architecture for 8 × 8 and 4 × 4 adaptive block-size transforms in H.264/AVC. By decomposing the 8 × 8 transform to basic 4 × 4 transforms, a unified architecture is designed for both 8 × 8 and 4 × 4 transform and the transform data-path can be efficiently reused for six kinds of transforms. i.e., 8 × 8 forward, 8 × 8 inverse, 4 × 4 forward, 4 × 4 inverse, forward-Hadamard, inverse-Hadamard transforms. Linear shift mapping is applied on the memory buffer to support parallel access both in row and column directions which eliminates the need for a transpose circuit. For reusable and configurable transform data-path, a multiple-stage pipeline is designed to reduce the critical path length and increase throughput. The design is implemented under UMC 0.18 um technology at 200 MHz with 13.651 K logic gates, which can support 1,920 × 1,088 30 fps H.264/AVC HDTV decoder.

Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor

This paper presents a cost-effective 2D-DCT processor based on a fast row/column decomposition approach. With a particular schedule, the processor does not require the transposed memory for 2D-DCT computing. We re-arrange the cosine coefficients of the first and second 1D-DCT transformations to keep DC-coefficient error free. The new architecture uses state-machines to generate cosine coefficients rather than ROM table, to save the memory cells and the address generator. For 8 × 8 DCT realization, the circuit only needs 36 adders without multipliers, and the whole chip uses about 19 k transistors. The chip area is about 4 mm ² using TSMC 0.35 um CMOS process. The circuit complexity is only 1/3 ~ 1/5 of the conventional DCT chips.     

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSE-BitSlice) arithmetic for hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The CSE-BitSlice technique has been applied to the design and implementation of 12 × 12 and 42 × 42 bit real multipliers, a complex multiplier, a 6-tap FIR filter, and a 5-point DFT circuit. For comparison purposes, circuit implementations of the same arithmetic and DSP functions have been carried out using Radix-4 Booth and CSA algorithms. Simulation results based on implementations using the Xilinx FPGA 5VLX330FF1760-2 device shows that the circuits based on the CSE-BitSlice techniques require fewer logic resources and yield higher throughput as compared to the CSA and Radix-4 Booth based circuits.     

Design and analysis of a super compact wide-band bandpass filter based on metamaterial resonators

In this paper, a novel compact wide-band bandpass filter (BPF) with a wide frequency range is presented. This filter consisting of a multi-mode resonator (MMR) and four metamaterial unit-cells benefits from a very compact size. Unit-cells based on a complementary spiral resonator (CSR) including a metallic via, improve both upper and lower stopband rejection and compensate the insertion loss (I.L) within the passband altogether. This wide-band filter presents a 3-dB bandwidth of 7.7 GHz, ranging from 3 GHz to 10.7 GHz and the Insertion loss is less than 0.7 dB over the passband. The measured results are in good agreement with both the full-wave electromagnetic simulation and the proposed circuit model results. The dimension of the fabricated filter is 0.128 λ × 0.1 λ (i.e., 5.6 × 4.4 mm²). This filter is considerably compact compared to the other wide-band bandpass filters with the same substrate.     

A New Current-Mode Current-Controlled Universal Filter Based on CCCII(±)

This paper proposes a new current-mode current-controlled single-input multiple-output type universal filter using non-inverting and inverting second generation current-controlled conveyors (CCCII(±)s). The proposed circuit employs four CCCII(±)s and two grounded capacitors, and it can simultaneously realize lowpass, bandpass, highpass, bandstop and allpass filter outputs. The circuit offers an independent electronic control of the natural angular frequency (ω ₀) and quality factor (Q) by means of adjusting the bias current of the CCCII(±)s. The parameter sensitivities are all very low. Moreover, a high Q-value filter can be easily obtained by adjusting the ratio of two bias currents. PSPICE simulation results at the natural frequency of 1.27 MHz are given to demonstrate the advantages of the proposed circuit. This work was supported by National Natural Science Foundation of China under No.60676021.     

基于LTCC技术的带通滤波器分析与设计

文章介绍了一种中心频率为2.45GHz的LTCC多层带通滤波器的设计方法。利用二阶耦合谐振带通滤波器的原型,通过一种分析合成带通滤波器的方法,将原型电路等效为4个L型匹配电路,设定其中两个匹配品质因子,经过推导并进行参数值取舍后,即可得到原型电路中所有元件的合成公式以及电路中各器件的参数值。利用三维电磁场仿真软件HFSS建立模型,可以将电磁模拟结果与电路仿真结果较好地吻合。最后采用标准LTCC工艺实现出尺寸为3.6mm×2.9mm×1.1mm的带通滤波器。     

Design a Low-Power H.264/AVC Baseline Decoder at All Abstraction Levels—A Showcase

In this paper, we propose a low-power VLSI implementation of H.264/AVC baseline decoder. A systematic methodology for power reduction is proposed and applied at various design abstraction levels. At the algorithm level, the computational complexity is optimized. At the architecture level, pipelining and parallelism are widely adopted to reduce the operating frequency; hierarchical memory organization optimizes power-hungry memory accesses; hardware sharing reduces the total switching capacitance. At the circuit level, the knowledge about signal statistics is exploited to reduce number of transitions; data dependent signal-gating and clock-gating are introduced which are dynamic techniques for power reduction; multiplications are reduced and optimized, while complex dividers are totally eliminated. At the physical level, cell sizing and layout are optimized for power efficiency. The VLSI implementation shows that with UMC 0.18 μm technology, the proposed design is able to decode realtime QCIF 30fps at 1.5 MHz. The decoder contains 169 k logic gates and 2.5 KB on-chip SRAM. The total chip area is 4.4 × 4.4 mm² in a CQFP 208 package. The measured power consumption is 973 μW @ 1.8 V and 293 μW @ 1.0 V. The low-power and realtime features make our design ideal for portable or mobile applications.     

A compact and high performance dual-band bandpass filter based on unbalanced composite right/left-handed transmission lines for WLANs applications

In this paper, a novel compact microstrip dual-band (DB) bandpass filter with high selectivity for wireless local area networks applications is proposed. The design procedure is based on unbalanced composite right/left-handed (UCRLH) transmission lines (TLs). The DB features can be achieved by unbalancing the CRLH transmission line. The necessary conditions to obtain a discontinuous transition between the left- and right-handed bands, intended to provide UCRLLH TL, are investigated. The application of this technique to design of compact DB filters is illustrated. The structure of the proposed DB filter is implemented by a series interdigital capacitor located between two microstrip lines that shorted to the ground plane by vias. The vias with microstrip lines acting as a shunt connected inductor while the series capacitor is realized by interdigital capacitor. The design procedure based on a simple equivalent circuit is also introduced. The proposed filter has advantages such as compact size, easy fabrication, high selectivity, low insertion loss, high return loss and, design flexibility. To validate the proposed technique, the proposed DB filter has been fabricated and tested. Good agreement has been found between simulation and measurement results. The total size of the proposed UCRLH DB filter is 0.17 λ_g × 0.048 λ_g, where λ_g is the guided wavelength of the lower pass-band. The size of the proposed DB filter is more compact in comparison with known similar filters.     

A Fast H.264 Intra Frame Encoder with Serialized Execution of 4 × 4 and 16 × 16 Predictions and Early Termination

This paper presents a fast H.264 intra frame encoder that processes a single macroblock of 1920 × 1080 size video in 334 cycles on average which is 20% faster than the previous best design. The speed-up is mainly achieved by early termination of either 4 × 4 intra prediction or 16 × 16 intra prediction. The executions of intra 4 × 4 and 16 × 16 predictions are serialized and the second prediction is terminated early by using the cost of the first prediction as the stop criterion. A simple and efficient algorithm by making use of spatial locality is proposed to select the mode that is processed first. To avoid the bubble cycles caused by this serialized execution of 4 × 4 and 16 × 16 predictions, the modified processing order presented in (Jung et al. 2008) is employed for intra 4 × 4 prediction in order to schedule dependent 4 × 4 blocks apart from each other. To further reduce the execution time of 4 × 4 prediction, neighboring pixels with the same value are grouped, and only one prediction mode in the group is evaluated. Experimental results show that the PSNR drop is 0.0619 dB and the bitrate increase is 0.842% when compared with the JM reference software. The additional hardware cost to support the proposed methods is less than eight thousand gates which are very small when compared with the hardware size of a whole intra frame encoder.     

Dual-band bandpass filter based on mixed electric and magnetic coupling of the hybrid quasi-lumped resonator

A novel compact dual-band bandpass filter based on mixed coupling of the hybrid quasi-lumped resonator is proposed. The filter is composed of two independent signal paths, each can generate one passband with two identical hybrid quasi-lumped resonators. The proposal combines the mixed electric and magnetic coupling technology with this novel resonator in the filter design. Analysis of the filter has been done with the equivalent circuit method. To validate the approach, a dual-band bandpass filter operating at 2.4/5.2 GHz has been fabricated. Both passbands were realised with mixed coupling. An additional transmission zero is generated at either passband. Final fabricated filter has good band skirt, low insertion loss and good out-of-band performance. Reasonable agreement is found between the calculated, simulated and measured results. The implementation area is 0.21λ_g × 0.12λ_g.     

HgCdTe Growth on 6 cm × 6 cm CdZnTe Substrates for Large-Format Dual-Band Infrared Focal-Plane Arrays

This paper describes molecular-beam epitaxy growth of mid-wavelength infrared (MWIR) and long-wavelength infrared (LWIR) dual-band device structures on large-area (6 cm × 6 cm) CdZnTe substrates. Wafer-level composition and defect mapping techniques were used to investigate the limiting mechanisms in improving the cutoff wavelength (λ _c) uniformity and reducing the defect density. Structural quality of epitaxial layers was monitored using etch pit density (EPD) measurements at various depths in the epitaxial layers. Finally, 640 × 480, 20-μm-pixel-pitch dual-band focal-plane arrays (FPAs) were fabricated to demonstrate the overall maturity of growth and fabrication processes of epitaxial layers. The MWIR/LWIR dual-band layers, at optimized growth conditions, show a λ _c variation of ±0.15 μm across a 6 cm × 6 cm CdZnTe substrate, a uniform low macrodefect density with an average of 1000 cm⁻², and an average EPD of 1.5 × 10⁵ cm⁻². FPAs fabricated using these layers show band 1 (MWIR) noise equivalent temperature difference (NETD) operability of 99.94% and band 2 (LWIR) NETD operability of 99.2%, which are among the highest reported to date.     

Fully differential CMOS CCII based on differential difference transconductor

This paper presents a new CMOS fully differential second-generation current conveyor (FDCCII). The proposed FDCCII is based on a fully differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit is operating at supply voltages of ±1.5 V, it has a total standby current of 380 μA. The application of the FDCCII to realize variable gain amplifier, fully differential integrator, and fully differential second order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS 0.35 μm technology.     

UWB Bandpass Filter Using Microstrip-to-CPW Transition With Broadband Balun

A novel ultra-wideband bandpass filter (BPF) is presented using a back-to-back microstrip-to-coplanar waveguide (CPW) transition employed as the broadband balun structure in this letter. The proposed BPF is based on the electromagnetic coupling between open-circuited microstrip line and short-circuited CPW. The equivalent circuit of half of the filter is used to calculate the input impedance. The broadband microstip-to-CPW transition is designed at the center frequency of 6.85 GHz. The simulated and measured results are shown in this letter.