Failure mechanisms of PVD Ta and ALD TaN barrier layers for Cu contact applications

PVD Ta-based and ALD TaN layers were studied as Cu diffusion barriers on poly-silicon, NiSi and CoSi₂ for Cu contact applications. The effectiveness of nanometer-thick layers, deposited in manufacturing compatible chambers on 200 and 300 mm wafers, is evaluated by detection of Cu-silicidation temperature using high temperature in situ XRD. It is found that Si diffuses into the α-Ta lattice for PVD barriers between 300 and 500 °C, and induces Ta silicidation at 600 °C. The agglomeration of TaSi₂ seems to be responsible for the damage of barrier continuity and cause subsequent Cu-silicidation. The growth of ALD TaN on different surfaces of NiSi was studied by XRF, RBS and XRR. The growth curves show excellent linearity as a function of thickness. TOF-SIMS shows closed layers after 60 ALD cycles. In situ XRD reveals that the failure temperature of 4 nm thick ALD layers is higher than 500 °C. It is found that the failure of 3 and 4 nm ALD TaN layers in Cu/barrier/NiSi stacks is a diffusion controlled process, with an activation energy Q of ∼2.2 eV and a pre-exponential factor D₀ of ∼3.8 × 10⁻³ cm²/s.     

Preparation and Characterization of TaN ALD Precursors

High purity organic-tantalum precursors for thin film ALD TaN were synthesized and characterized.Vapor pressure and thermal stability of these precursors were studied.From the vapor pressure analysis,it was found that TBTEMT has a higher vapor pressure than any other published liquid TaN precursor,including TBTDET,TAITMATA,and IPTDET.Thermal stability of the alkyl groups on the precursors was investigated using a 1H NMR technique.The results indicated that the tertbutylimino group is the most stable group on TBTDET and TBTEMT as compared to the dialkylamido groups.Thermal stability of TaN precursors decreased in the following order:TBTDET ＞ PDMAT ＞ TBTEMT.In conclusion,precursor vapor pressure and thermal stability were tuned by making slight variations in the ligand sphere around the metal center.     

TaN薄膜原子层淀积

我们成功合成了TaN薄膜原子层淀积的高纯有机钽先驱物并使其特性化,同时对这些先驱物的汽压和热稳定性进行了研究。根据汽压分析发现,TBTEMT比所有其它已发表的液体TaN先驱物(包括TBTDET、TAITMATA和IPTDET)具有更高的汽压。用1HNMR技术研究了这些烷基先驱物的热稳定性。结果表明,与乙二烯基先驱物相比,对于TBTDET和TBTEMT材料,特丁基群是最稳定的基群。TaN先驱物热稳定性按以下次序下降:TBTDET>PDMAT>TBTEMT。最后,通过对金属中央周围的配合基体进行轻微的调整使先驱物汽压和热稳定性处于良好的状态。     

Mobility enhancement in TaN metal-gate MOSFETs using tantalum incorporated HfO/sub 2/ gate dielectric

TaN metal-gate nMOSFETs using HfTaO gate dielectrics have been investigated for the first time. Compared to pure HfO/sub 2/, a reduction of one order of magnitude in interface state density (D/sub it/) was observed in HfTaO film. This may be attributed to a high atomic percentage of Si-O bonds in the interfacial layer between HfTaO and Si. It also suggests a chemical similarity of the HfTaO-Si interface to the high-quality SiO/sub 2/-Si interface. In addition, a charge trapping-induced threshold voltage (V/sub th/) shift in HfTaO film with constant voltage stress was 20 times lower than that of HfO/sub 2/. This indicates that the HfTaO film has fewer charged traps compared to HfO/sub 2/ film. The electron mobility in nMOSFETs with HfO/sub 2/ gate dielectric was significantly enhanced by incorporating Ta.     

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.     

Cu contact on NiSi substrate with a Ta/TaN barrier stack

The thermal and electrical stabilities of Cu contact on NiSi substrate with and without a Ta/TaN barrier stack in between were investigated. Four-point probe (FPP), X-ray diffraction (XRD), scanning electron microscopy (SEM), depth-profiling X-ray photoelectron spectroscopy (XPS), and Schottky barrier height (SBH) measurement were carried out to characterize the diffusion barrier properties. The SBH measurement provides a very sensitive method to characterize the diffusion barrier properties for the copper contact on NiSi/Si. The results show that the Ta/TaN stack can be both thermally and electrically stable after annealing at 450 °C for 30 min and it will have a potential application as a diffusion barrier for Cu contact on NiSi.     

TDDB and polarity-dependent reliability of high-quality, ultrathin CVD HfO/sub 2/ gate stack with TaN gate electrode

In this letter, we present a comprehensive study on longterm reliability of ultrathin TaN-gated chemical vapor deposition gate stack with EOT=8.5-10.5. It is found that, due to the asymmetric band structure of HfO/sub 2/ gate stack with an interfacial layer, the HfO/sub 2/ gate stack shows polarity-dependent leakage current, critical defect density, and defect generation rate, under gate and substrate injection. However, no such polarity dependence of time-to-breakdown (T/sub BD/) is observed when T/sub BD/ is plotted as a function of gate voltage. The 10-year lifetime of an HfO/sub 2/ gate stack is projected to be Vg=-1.63 V for the equivalent oxide thickness (EOT) =8.6 and Vg=-1.88 V for EOT=10.6 at 25/spl deg/C. These excellent reliability characteristics are attributed to reduced leakage current of HfO/sub 2/ gate stack with physically thicker films that result in larger critical defect density and Weibull slope to that of SiO/sub 2/ for the same EOT. However, at 150/spl deg/C, and with area scaling to 0.1 cm/sup 2/ and low percentile of 0.01%, the maximum allowed voltages are projected to Vg=-0.6 V and -0.75 V for EOT of 8.6, and 10.6, respectively.     

Pt-Germanide Schottky source/drain Germanium p-MOSFET with HfO/sub 2/ gate dielectric and TaN gate electrode

Schottky source/drain (S/D) transistors using Pt-germanide and HfO/sub 2//TaN gate stack are fabricated on Ge-substrate with conventional self-aligned top-gate process. It was found that Pt-germanide provides promising properties for p-MOSFET: negative effective hole barrier height, low resistivity, atomically sharp junction with Ge with good morphology. Pt-germanide Ge-p-MOSFETs showed well-behaved I/sub D/-V/sub D/ characteristics and much suppressed I/sub off/ compared to Ni-germanide and conventional heavily doped S/D MOSFETs.     

Improved device performance and reliability in high /spl kappa/ HfTaTiO gate dielectric with TaN gate electrode

The device performance and reliability of higher-/spl kappa/ HfTaTiO gate dielectrics have been investigated in this letter. HfTaTiO dielectrics have been reported to have a high-/spl kappa/ value of 56 and acceptable barrier height relative to Si (1.0 eV). Through process optimization, an ultrathin equivalent oxide thickness (EOT) (/spl sim/9 /spl Aring/) has been achieved. HfTaTiO nMOSFET characteristics have been studied as well. The peak mobility of HfTaTiO is 50% higher than that of HfO/sub 2/ and its high field mobility is comparable to that of HfSiON with an intentionally grown SiO/sub 2/ interface, indicative of superior quality of the interface and bulk dielectric. In addition, HfTaTiO dielectric has a reduced stress-induced leakage current (SILC) and improved breakdown voltage compared to HfO/sub 2/ dielectric.     

Short-channel metal-gate TFTs with modified Schottky-barrier source/drain

A thin active layer, a fully silicided source/drain (S/D), a modified Schottky-barrier, a high dielectric constant (high-/spl kappa/) gate dielectric, and a metal gate are integrated to realize high-performance thin-film transistors (TFTs). Devices with 0.1-/spl mu/m gate length were fabricated successfully. Low threshold voltage, low subthreshold swing, high transconductance, low S/D resistance, high on/off current ratio, and negligible threshold voltage rolloff are demonstrated. It is thus suggested for the first time that the short-channel modified Schottky-barrier TFT is a solution to carrier out three-dimension integrated circuits and system-on-panel.     

Performance improvement of self-aligned HfO2/TaN and SiON/TaN nMOS transistors

Direct-etched HfO₂/TaN nMOS transistors were fabricated. The performance of the transistors with aggressively scaled EOT is comparable or better than that of SiO₂/poly transistors. The performance enhancement requires a combination of EOT scaling and an appropriate interface layer control. The performance of the direct-etched TaN gated HfO₂ based transistors is also compared to the performance of similar TaN gated SiON based transistors. It is observed that for equal g_m the leakage is lower for HfO₂ based transistors, despite the lower EOT for the HfO₂ based devices.     

在双镶嵌铜互联中O.13微米器件生成用的基于PVD和ALD阻挡层的先进技术

1. Introduction The requirement of minimal bottom coverageand thick sidewall coverage for PVD-based films forlow via resistance and improved stress migration isnot easy to achieve with traditional depositionmethods. Modern I-PVD techniques give high bot-tom coverage, due to the ionized component of thedeposition flux. Sidewall coverage tends to be low,which is mainly due to off-normal deposition fluxand a less than unity sticking coefficient.     

Chemical studies of CVD Cu deposited on Ta and TaN barriers under various process conditions

Contamination in the matrix of CVD copper films and at the interface between CVD copper films and barrier layers has been characterized using XPS, SIMS, XRD and RGA. Contamination in the CVD copper matrix has been found to increase with increasing precursor flow rate and with decreasing wafer temperature. Interfacial contamination has been investigated in an attempt to quantitatively define acceptable levels of contamination and ultimately reduce the effect of these contaminants on the integrated film stack. Sputtered copper flash layers for CVD copper deposition are also shown as highly effective for reducing the levels and effects of incorporated contamination.     

Improved Electrical Properties of ALD Hfx Zr1 − xO2 Dielectrics Deposited on Ultrathin PVD Zr Underlayer

The impact of ultrathin metal underlayer on physical and electrical properties of Hf _x Zr_{1- x} O₂(x=~0.4) after high-temperature processing was investigated. An ~5-Aring Zr, ~5-Aring Hf, ~10-Aring Hf metal layer was sputter deposited prior to Hf _x Zr_{1- x} O₂ growth. Cross-sectional transmission electron microscopy and secondary ions mass spectrometry analysis confirmed no Zr or Hf silicide formation between the high-k film and Si substrate even after 1000degC processing. No significant increase in equivalent oxide thickness or gate leakage current is observed on devices with metal underlayer. Furthermore, devices with a 5-Aring-thick Zr underlayer exhibited lower threshold voltage, higher mobility, and improved charge trapping characteristics.     

Cu contact on NiSi/Si with thin Ru/TaN barrier

Thin Ru(5 nm)/TaN(15 nm) bi-layer was sputtered on the NiSi/Si substrate as a diffusion barrier in the copper contact structure. The barrier properties were investigated through X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), energy dispersive X-ray (EDX) and electrical measurement. The whole Cu/Ru/TaN/NiSi/Si structure has a good thermal stability until after annealing at 450 °C. The Schottky barrier measurement shows that the leakage current increases after 450 °C annealing and after 500 °C annealing the barrier fails. Failure mechanism of the barrier stack is discussed.     

Electrical and reliability characterization of metal-gate/HfO2/Ge FET’s with Si passivation

Field-effect transistors with metal gate and HfO₂ gate dielectric on silicon-passivated germanium substrate are studied. Capacitance-Voltage characteristics show lower gate capacitance at negative gate voltages, irrespective of the device channel polarity. Possible mechanisms for this asymmetry are discussed. Reliability of the metal/high-k gate stack on sub-micron p-channel transistors is evaluated. Time-dependent dielectric breakdown analysis indicates comparable gate-stack quality on germanium and silicon substrates.     

High-/spl kappa//metal-gate stack and its MOSFET characteristics

We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal-gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//metal-gate CMOS transistors with desirable threshold voltages.     

Aggressively scaled ultra thin undoped HfO/sub 2/ gate dielectric (EOT<0.7 nm) with TaN gate electrode using engineered interface layer

The ultrathin HfO/sub 2/ gate dielectric (EOT<0.7 nm) has been achieved by using a novel "oxygen-scavenging effect" technique without incorporation of nitrogen or other "dopants" such as Al, Ti, or La. Interfacial oxidation growth was suppressed by Hf scavenging layer on HfO/sub 2/ gate dielectric with appropriate annealing, leading to thinner EOT. As the scavenging layer thickness increases, EOT becomes thinner. This scavenging technique produced a EOT of 7.1 /spl Aring/, the thinnest EOT value reported to date for "undoped" HfO/sub 2/ with acceptable leakage current, while EOT of 12.5 /spl Aring/ was obtained for the control HfO/sub 2/ film with the same physical thickness after 450/spl deg/C anneal for 30 min at forming gas ambient. This reduced EOT is attributed to "scavenging effect" that Hf metal layer consumes oxygen during anneal and suppresses interfacial reaction effectively, making thinner interface layer. Using this fabrication approach, EOT of /spl sim/ 0.9 nm after conventional self-aligned MOSFETs process was successfully obtained.     

NBTI reliability on high-k metal-gate SiGe transistor and circuit performances

Negative-bias temperature instability (NBTI) on high-k metal-gate SiGe p-channel MOSFETs has been examined. SiGe p-MOSFETs shows reduced interface states and enhanced NBTI reliability compared to their Si p-channel control devices as evidenced by experimental data. Impact of NBTI reliability on digital and RF circuits has been also examined using extracted fresh and stressed BSIM4 model parameters in circuit simulation. High-k metal-gate SiGe pMOSFETs demonstrate less inverter pull-up delay, smaller noise figure of a cascode low-noise amplifier, and larger output power and power-added efficiency than their Si counterparts when subject to NBTI stress.     

High-field mobility metal-gate/high-κ Ge n-MOSFETs with small equivalent-oxide-thickness

We fabricated high performance gate-last TaN/La₂O₃/SiO₂ on Ge n-MOSFET. Small equivalent-oxide-thickness (EOT) of 1.9-nm and high-field mobility of 258 cm²/V s at 0.75 MV/cm were obtained, which were attributed to the thin SiO₂-like barrier layer and low process temperature to prevent interfacial reaction during post-deposition annealing (PDA).