基于氮化镓特征的高效功率放大器拓扑设计

基于对功率三极管实际输出端特性的考虑,提出一种易实现的高效率功放拓扑结构,并通过负载控制理论进行更贴合实际的理论分析。基于CREE公司GaN HEMT CGH40010仿真,在输入为25 dBm,偏置为28 V,带宽在2.98 GHz~3.02 GHz时,输出功率高于38.5 dBm,功率附加效率优于70%,并且在3 GHz时功率附加效率达到73.4%。在15 V~30 V的偏置范围内,漏极效率达到70%以上,仿真结果很好地验证了拓扑的可行性。     

微带线E类功率放大器的设计与实现

E类功率放大器作为开关模式放大器一种,其理想效率为100%。一种简单微带线拓扑网络的E类功率放大器被提出,这种微带线负载网络不仅满足E类功率放大器工作模式的特殊要求,而且对高次谐波有很好的抑制性,同时通过增加合适的偏置微带线可以拓宽放大器的工作带宽。采用ADS软件仿真电路,并在1GHz频率点电路实现了输出功率为4W,漏极效率为73.4%,其中漏极效率效率在63%以上的电路带宽为200MHz。     

基于F类和逆F类的双模式双频带功率放大器

应用氮化镓高电子迁移率晶体管设计并实现了一种基于F类和逆F类工作模式的双频段功率放大器。首先，分别讨论了F类和逆F类工作模式在理想晶体管和实际晶体管中的差异，结合动态负载线和电压电流波形，对实际晶体管功率和效率下降的原因作了深入分析。在此基础上，提出一种在双频段分别实现F类和逆F类工作模式的输出匹配电路。基于该匹配电路，仿真设计了一款双模式、双频带功率放大器，并进行了实物加工和性能测试。实测结果表明，在L和S频段200 MHz带宽范围内，功放输出功率分别大于41.3 dBm和41.2 dBm，漏极效率分别高于72%和69%，其峰值功率和效率在L频段为41.7 dBm和75.5%，在S频段为41.3 dBm和69.5%。实测和仿真结果吻合度高，证明了提出的设计方法的正确性和有效性。     

高效率开关F3/E类功率放大器

介绍了一种高效F3/E类功率放大器的设计方法,该放大器将F类功率放大器的谐波控制电路引入逆E类功率放大器的负载网络,以改善放大器性能。此电路结构提升了放大器的功率输出能力,降低了电路对功率放大器管器件漏极耐压特性的要求,增强了器件工作时的安全性。详细阐述了该放大器的设计过程,并给出了负载网络各器件的最佳设计取值方程。选用GaNHEMT器件研制了S频段F3/E类功率放大器测试电路。实测结果表明该放大器在驱动功率为27 dBm时,可获得40.3 dBm的输出功率,具有13.3 dB增益,工作效率高达78.1%,功率附加效率为75.2%。实测结果与仿真结果吻合,验证了设计方法的正确性。     

F类与逆F类功率放大器的效率研究

为了对F类与逆F类功率放大器的效率进行研究,首先从理论方面对两种放大器工作模式各自的效率进行了计算。通过计算可以看出,在相同的输出功率下,因为晶体管导通内阻的存在,逆F类功率放大器的效率优于F类功率放大器。再通过软件仿真设计F类和逆F类功率放大器,在相同的输出功率下,逆F类功率放大器的最高漏极效率为91.8%,F类功率...     

串联偏置迭堆式毫米波功率放大器的设计

设计了一种串联迭堆式偏置供电的毫米波功率放大器,其漏极供电电压高达+24V。该功率放大器共包含4个单芯片功率放大模块,每个模块承受+6V左右漏极电压。功率合成网络采用一分四的E面波导功分器,模块与功分网络间相互绝缘连接。该功率放大器最终实现的性能指标是:在直流偏置点(+24V,4.2A)条件下,功率放大器在频段26～30GHz内其连续波饱和输出功率大于42.1dBm,功率附加效率大于11.0%。提出了一种毫米波发射机功率输出部分新的构架形式,在模块级别对功率放大器串联馈电进行了首次尝试。     

一种55 nm CMOS 5 GHz高效E类射频功率放大器

为了减小功率放大器的功率损耗、提高功率附加效率,基于TSMC 55 nm CMOS工艺,设计了一种工作频率为5 GHz的高效率E类射频功率放大器。采用包含驱动级的两级电路结构,提高了电路的功率增益。对负载回路进行优化设计,改善了漏极电压与电流波形交叠的问题,进而提升了效率,同时降低了漏极电压的峰值,缓解了晶体管的击穿压力。仿真结果表明,电源电压为2.5 V时,该放大器的输出功率为21.2 dBm,功率附加效率为53.1%。     

C波段高效率逆F类GaN MMIC功率放大器

为了解决晶体管寄生参数对逆F(F-1)类功率放大器效率的影响,采用了一种新型的输出谐波控制结构。首先,设计二次和三次谐波控制电路,同时将直流偏置电路加入二次谐波控制电路,降低了电路设计的复杂度。其次,为了解决寄生参数对F-1类功放本征漏极端阻抗的影响,采用一段串行微带线进行寄生补偿。最后,通过微带线和电容进行基波和负载之间的匹配。为验证方法的有效性,采用0.25 μm氮化镓高电子迁移率晶体管(GaN HEMT)工艺,设计了一款工作在5.7 GHz~6.3 GHz的F-1类微波集成电路功放。版图后仿真结果显示,F-1类功放的漏极效率DE为57.2%~62.3%,功率附加效率PAE为51.8%~57.4%,饱和输出功率为39.0 dBm~40.4 dBm,增益为9.0 dBm~10.4 dBm。版图面积为3.2×1.7 mm²。     

逆F类放大器漏极电压波形研究

为了更清晰地了解逆F类功率放大器通过规整漏极电压和电流波形实现高效率的本质,对其漏极电压波形进行了理论分析和仿真验证。结果表明,在仅考虑二、三次谐波,且当谐波比例k=1/4时,v(θ)波形最平坦,最近似于半正弦波。利用电磁软件仿真设计并制作了一款k=0.271的逆F类功率放大器,经测试在输出功率为36.33 dBm时,功率附加效率达到了71%。     

F类功率放大器漏极电压研究

F类功率放大器实现高效率的基本原理,是利用输出滤波器控制漏极输出的电压或电流波形。基于这一点,文中首先理论分析了在不同谐波比例下的漏极电压波形,然后利用电磁仿真软件进行验证。结果表明,仅有三次谐波和基波组合在一起时,当三次谐波和基波电压比K=0.111时,漏极电压波形最平坦;当K接近0.4时,漏极电压波形趋于方波。最后选择合适的谐波比例,设计了一款功率附加效率最大值达到88.074%的F类功率放大器。     

Investigation into SiGe HBT class E/F PA efficiency at 2 GHz for VDD from 1 to 1.8 V

This letter presents a 2-GHz SiGe heterojunction bipolar transistor fully integrated class E/F power amplifier (PA) design operating at low supply voltage. A maximum measured power added efficiency (PAE) of 39% is achieved for a supply voltage of 1.8V. At 1V, a maximum PAE of 36% is measured. The PA was fabricated using an advanced 0.18-/spl mu/m BiCMOS process.     

高效率Class F功率放大器的设计

本文基于InGaP/GaAs HBT(HBT为异质结双极晶体管)工艺设计了一款高效率的Class F功率放大器。文中首先描述了F类功率放大器的特点和电路原理,然后对放大器的设计过程如匹配电路设计技术、谐波抑制对功率效率的影响,以及偏置电路的设计等问题做了详细的讨论。测试结果表明,设计的功率放大器在电源电压为5V,输出功率为37dBm时,效率达68%。     

A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS

A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or RF enhancements. With a 1 V power supply, the PA achieves 24.3 dBm maximum output power at a peak drain efficiency of 27% and 20.5 dBm output power at the 1 dB compression point.     

Low voltage, high efficiency GaAs Class E power amplifiers forwireless transmitters

A Class E power amplifier for mobile communications is presented. The advantages of Class E over Class B, Class C, and Class F power amplifiers in a low voltage design are discussed. A fully integrated Class E power amplifier module operating at 835 MHz is designed, fabricated, and tested. The circuit is implemented in a self-aligned-gate, depletion mode 0.8-μm GaAs MESFET process. The amplifier delivers 24 dBm of power to the 50-Ω load with a power added efficiency greater than 50% at a supply voltage of 2.5 V. The power dissipated in the integrated matching networks is 1.5 times the power dissipated in the transistor     

应用于无线传感器网络的功率放大器的设计

给出一种基于TSMC 0.18 μm RF CMOS工艺,应用于无线传感器网络的2.4 GHz 功率放大器的设计.该功率放大 器工作频率范围为2.4 GHz～2.4835 GHz,采用全差分AB类共源共栅电路结构,使用功率控制技术以节省功耗,当输入信号 功率-12.5 dBm时,输出功率在-10.4 dBm至5.69 ...     

A highly efficient class-EF<Subscript>2</Subscript> power amplifier in GaAs pHEMT technology

This paper presents a highly efficient class-EF₂ power amplifier in GaAs pHEMT technology with high output power. Drain swing voltage of class-E power amplifier (PA) imposes a restriction on its output power. In this work, using a combination of class-E and F relaxes this limitation which may help in increasing DC supply voltage. Higher DC supply voltage of class-EF₂ PA leads to increased output power and efficiency, as output power is proportional to supply voltage. In addition, higher supply voltage permits PA to work under lower current which can cause to reduce power dissipation. Proposed class-EF₂ PA is implemented in a single recess AlGaAs–InGaAs pHEMT technology with 0.25-µm gate length; power added efficiency of 52% at 31 dBm output power is achieved at 1.8 GHz.     

A 900 MHz,21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

A two-stage differential linear power amplifier(PA) fabricated by 0.18μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power,efficiency and harmonic performance.Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency(PAE) is 35.4%,the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled.The total area with ESD protected PAD is 1.2×0.55 mm~2.Sy...     

A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 $mu$m CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 802.16e signals.      

A Two-Point Modulation Technique for CMOS Power Amplifier in Polar Transmitter Architecture

A two-point modulation technique is presented that improves the performance of nonlinear power amplifiers (PAs) in polar transmitters. In this scheme, the output amplitude modulation is performed by controlling the current of the PA. The current control technique enables the PA to provide wideband amplitude modulation, as well as high power control dynamic range. In addition, the supply voltage of the PA is adjusted based on the output power level. The voltage supply adjustment substantially improves the effective power efficiency of the PA. The voltage supply control is performed using a second-order sigma-delta dc-dc converter, which presents an efficiency of over 95% in its operational range. The PA operates at 900 MHz with maximum output power of 27.8 dBm and power efficiency of 34% at maximum output power. The proposed PA achieves 62-dB power control dynamic range with amplitude modulation bandwidth of over 17.1 MHz. The circuits are fabricated in a CMOS 0.18 mum process with a 3.3-V power supply.     

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-$mu$ m 2.5-V standard I/O FETs in a 0.13- $mu$m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.