Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs

A model development methodology for complex shaped on-wafer interconnects is presented. The equivalent circuit of the entire interconnect is obtained by cascading basic subsegment models. The extracted parameters are formulated into empirical expressions. Thus, the proposed model can be easily incorporated with commercial electronic design automation (EDA) tools. The accuracy of the model is validated by the on-wafer measurements up to 20 GHz.     

Scalable Model of On-Wafer Interconnects for High-Speed CMOS ICs

This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two-pi blocks together, the lumped model can characterize the distributed effects. Besides, the elaborately proposed model characterizes the frequency-variant characteristics with frequency-independent components. Thus, the model can be easily plugged into commercial computer-aided design tools. By adopting a newly invented optimization algorithm, namely, particle swarm optimization (PSO), the model parameters are extracted and formulated as empirical expressions. Therein, with each set of the geometrical parameters, the interconnect behaviors can be accurately predicted. The accuracy of the model is validated by comparisons with the on-wafer measurements up to 30 GHz. Moreover, the scalability of the proposed model is also discussed     

Experimental investigation of the temperature dependence of GaAsFET equivalent circuits

Accurate 13-element temperature-dependent RF equivalent circuits have been extracted from on-wafer S-parameter measurements of ion implanted and epitaxially grown recess-gate MESFETs and HEMTs at many biases for temperatures from -70 to +110°C. The variations in each equivalent circuit element are expressed by a linear function of temperature. The temperature coefficients are bias- and technology-dependent. These data can be used to predict RF circuit performance variations with temperature. It is used to deduce the temperature dependence of physical factors such as electron mobilities and saturated velocities and the Schottky-barrier height     

光探测器芯片小信号等效电路模型的建立

提出了一种光探测器芯片小信号等效电路模型及其建立方法.首先根据光探测器的物理结构确定其等效电路模型,模型考虑了影响光探测器高频性能的主要因素.然后精确测量了光探测器芯片的S参数,通过遗传算法对测量的S参数进行拟合,最终计算出模型的各个参量.在130MHz～20GHz范围内的实验结果表明,模型仿真结果与测量结果相吻合,证明了建模方法的可靠性.该模型有效地模拟了光探测器芯片的高频特性,利用该模型可以对光探测器及相应光电集成器件进行电路级仿真和优化.     

A universal de-embedding procedure for the "on-wafer" GHz probing

A novel de-embedding procedure for "on-wafer" GHz probing is presented. The parasitic effects arising from the bond-pads are modeled generally by two-port networks. Thus, no equivalent circuit details are required. Even the transmission line effects occurring at extremely high frequencies can be taken into account in this model.<>     

A three-step method for the de-embedding of high-frequencyS-parameter measurements

The authors propose a general method of deembedding S-parameter measurements of the device-under-test (DUT) for which typical parasitics associated with probe pads and interconnect-metal lines can be deembedded from the measurement. The DUT is the analog silicon bipolar junction transistor including the pad and interconnects. This method includes the subtraction of the parasitic shunt y-parameters of the on-wafer open calibration pattern as well as the subtraction of the parasitic series z-parameters on the on-wafer open circuit which are taken from measurements of the short and through circuits. It is demonstrated that the calculated power loss for the pad and interconnect parasitics can be comparable to the power consumption of the advanced bipolar transistor at high frequencies (⩾10 GHz). A knowledge of the magnitude and type of parasitic deembedding circuit elements can aid the device engineer in the analysis of the error associated with deembedding     

有耗互连线频变电感提取及等效电路模型

采用二维电感模型，计算了带接地导体的有耗互连线的频变阻抗。阻抗函数用分式多项式近似，并表达为串接的并联电阻、电感的福斯特电路形式。考虑互连线分布电容参数，并根据多个频点阻抗值，用有限数量极点，综合得到互连线单位长度的等效电路模型。采用该模型进行互连线时域响应分析，其结果与改进特征法结果吻合较好，且便于与其他电路模型结合，进行大规模电路的时域分析。     

Microwave Noise Characterization of GaAs MESFET's: Evaluation by On-Wafer Low-Frequency Output Noise Current Measurement

A simplified noise equivalent circuit is presented for submicron-gate-length MESFET's in the common-source configuration, consisting of five linear circuit elements: the gate-to source capacitance C/sub gs/, the total input resistance R/sub T/, the transconductance g/sub m/, the output resistance R/sub 0/, and a noise current source of spectral density S/sub io/ at the output port. All of these elements can be determined by on-wafer measurements, and the noise current can be measured at a low frequency. The minimum noise figure of the device calculated from this model, as well as the bias and frequency dependence of the noise figure, is shown to be in agreement with microwave noise figure measurements. Thus a technique has been established for determination of the minimum noise figure of a device solely by on-wafer measurements rather than by the usual microwave measurements. The proposed technique can be employed rapidly, conveniently, without the need for tuning, and at the wafer stage of device fabrication.     

A 17.5-GHz 3-bit phase-shift receive MMIC-fabrication and testresults

A high-yield, FET gate fabrication technology is described. The main advantage of this processing approach is that it permits fabrication of devices with gate lengths of less than 0.5 μm using standard optical photolithography without recourse to deep UV or electron-beam lithography. The process is simple and easy to implement in a manufacturing environment. Exceptionally good gate-length control, typically 10% for a 0.4-μm-long gate, is demonstrated. Yield of a 300-μm-wide FET, designed for use in a gain block and in a switch, is found to be 89% on average. Data on wafer-to-wafer and on-wafer variations in device DC and RF parameters and equivalent circuit values are presented. Typical standard deviations are in the 5-10% range. This process technology has been used to fabricate a 17.5-GHz, 3-b phase-shift receive monolithic microwave integrated circuit (MMIC) of moderately high complexity. Statistics of RF data on 704 such devices, fabricated over a period of two years, are presented. It is shown that such MMICs can be fabricated with yields sufficient for prototype active phased-array antenna applications     

A practical approach to model long MIS interconnects in VLSI circuits

In this paper, a practical approach to model metal-insulator-semiconductor (MIS) interconnects is presented, with focus on the microstrip configuration. Starting from a one-dimensional (1-D) electromagnetic field analysis, we first extend the validity range of some closed-form expressions from 1-D to two-dimensional (2-D) and present an original RLCG-B model with five equivalent circuit parameters. These parameters, which depend on two effective widths of the physical metal strip, can be frequency dependent because of the skin effect and the dielectric losses. The original RLCG-B model is then modified and implemented with seven frequency-independent circuit parameters. These parameters are computed by analytical equations. Numerical simulations are used to validate the original and modified RLCG-B models. A formula to allow comparison of various interconnect models in the time domain is proposed. Comparisons based on this formula are presented for a single transmission line with source resistance, R/sub S/, and load capacitance, C/sub L/. Such comparisons are more meaningful in VLSI applications than comparisons of characteristics derived from swept-frequency per-unit-length parameters.     

Performance Evaluation and Equivalent Model of Silicon Interconnects for Fully-Encapsulated RF MEMS Devices

This paper aims to demonstrate the utility of silicon interconnects for radio-frequency (RF) microelectromechanical system (MEMS) devices that are packaged using a wafer-scale encapsulation process. Design and fabrication steps for the packaged interconnects are described. Measurement results show that encapsulated devices can be operated at frequencies up to 6 GHz with less than 1 dB insertion loss from the through-package silicon interconnects. This paper also describes a simple and accurate lumped-element model for simulating the performance of packaged silicon interconnects. The model is verified with S-parameter measurements from 50 MHz to 6 GHz. The modeling method and extracted values are intended to aid in the design and simulation of RF MEMS devices packaged using this technology.      

The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

With the continuous advancement of semiconductor technology,the interconnects crosstalk has had a great influence on the performances of VLSI circuits.To date,most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed.First of all,an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes.The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model.Secondly,the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique andABCD parameter matrix approach at local level,intermediate level and global level,respectively.Moreover,the experimental results show that the CMS interconnects have lesser noise peak,noise width and noise amplitude than the VMS interconnects in the same cases,and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits.It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.     

Electromigration reliability of interconnections in RF low noise amplifier circuit

With the continuous increase of the circuit complexity and the scaling down of the device size, electromigration (EM) failure in the interconnects has become the determining factor for circuit reliability. Most of the EM circuit simulators in the literature are at 2D level. The application of 2D simulators is limited as the actual physical implementation of the circuit in a wafer is indeed 3D in nature, and is much more complicated than 2D. In this paper, we construct a complete 3D circuit model of a RF low noise amplifier (LNA) circuit, including both the intra- and inter-block interconnects. Electric-thermal-structural simulations are performed and the modifications that help to enhance the EM reliability of the circuit are carried out based on the simulation results.     

射频CMOS平面螺旋电感2-π等效电路模型参数的提取

从有理分式拟合方法出发,提出了用于射频CMOS平面螺旋电感2-π等效电路模型参数提取的新方法.通过比较提参后等效电路给出的S参数和实验测量的S参数,证明该方法的精度很高.此外,提参的策略非常直接,因此容易在CAD里面编程实现.提参得到的等效电路模型对于射频电路设计者来说也是非常有用的.     

Deep-submicrometer DC-to-RF SOI MOSFET macro-model

We present a submicrometer RF fully depleted SOI MOSFET macro-model based on a complete extrinsic small-signal equivalent circuit and an improved CAD model for the intrinsic device. The delay propagation effects in the channel are modeled by splitting the intrinsic transistor into a series of shorter transistors, for each of which a quasistatic device model can be used. Since the intrinsic device model is charge-based, our RF SOI MOSFET model can be used in both small and large-signal analyses. The model has been validated for frequencies up to 40 GHz and effective channel lengths down to 0.16 μm     

晶圆上测试射频系统级芯片的挑战(英文)

随着无线通讯产业推动芯片集成度的不断提高,系统级封装(SIP)和多芯片组件(MCM)被更多采用,射频系统级芯片(RF-SOC)器件的良品测试已成为一大挑战。这些器件与传统的单晶片集成电路相比,具有更高的封装成本,并且由于采用多个晶片,成品率较低。其结果是进行晶圆上综合测试的成本远超过最终封装后测试器件的成本。此外,一些IC制造商销售裸晶片以用于另一些制造商的SIP和MCM中,这就要求发货的产品必须是良品。以蓝牙射频调制解调芯片为例,讨论了RF-SOC器件良品晶片(KGD)的测试难点和注意事项。对此样品,除了在晶圆上进行射频功能测试的难点,还有同时发射和测量数字、射频信号的综合问题。此外对被测器件(DUT)用印制线路板布线的难点,包括晶圆探针卡的设置及装配进行探讨。还介绍了选择探针测试台、射频晶圆探针卡和自动测试设备(ATE)时需考虑的因素。并以晶圆上测试的系统校正,包括难点和测试方法,作为结尾。这颗蓝牙射频调制解调芯片的实际测试数据也会被引用,以佐证和加深文章中的讨论。     

Wiring Effect Optimization in 65-nm Low-Power NMOS

This letter investigates the wiring effect on RF performance in advanced 65-nm low-power CMOS technology. New designs are proposed to minimize the parasitic resistances and capacitances associated with the interconnects in the transistor. Compared with the standard multifinger devices provided by the foundry, the device with the optimized wiring parasitic capacitances and resistances presents improvement up to $sim$ 21% for $f_{T}$ (increased from 89 to 108 GHz) and $sim$22% for $f_{max}$ (increased from 130 to 159 GHz), respectively. The extracted equivalent circuit model parameters indicate that the proposed approach can effectively minimize the parasitic effects leading to improved RF performance of the advanced MOSFETs.      

Modeling, Analysis, and Design of Graphene Nano-Ribbon Interconnects

Graphene nanoribbons (GNRs) are considered as a prospective interconnect material. A comprehensive conductance and delay analysis of GNR interconnects is presented in this paper. Using a simple tight-binding model and the linear response Landauer formula, the conductance model of GNR is derived. Several GNR structures are examined, and the conductance among them and other interconnect materials [e.g., copper (Cu), tungsten (W), and carbon nanotubes (CNTs)] is compared. The impact of different model parameters (i.e., bandgap, mean free path, Fermi level, and edge specularity) on the conductance is discussed. Both global and local GNR interconnect delays are analyzed using an RLC equivalent circuit model. Intercalation doping for multilayer GNRs is proposed, and it is shown that in order to match (or better) the performance of Cu or CNT bundles at either the global or local level, multiple zigzag-edged GNR layers along with proper intercalation doping must be used and near-specular nanoribbon edge should be achieved. However, intercalation-doped multilayer zigzag GNRs can have better performance than that of W, implying possible application as local interconnects in some cases. Thus, this paper identifies the on-chip interconnect domains where GNRs can be employed and provides valuable insights into the process technology development for GNR interconnects.      

A simple four-port parasitic deembedding methodology for high-frequency scattering parameter and noise characterization of SiGe HBTs

A new four-port scattering parameter (S-parameter) and broad-band noise deembedding methodology is presented. This deembedding technique considers distributed on-wafer parasitics in the millimeter-wave band (f>30GHz). The procedure is based on simple analytical calculations and requires no equivalent circuit modeling or electromagnetic simulations. Detailed four-port system analysis and deembedding expressions are derived. Comparisons between this new method and the industry-standard "open-short" method were made using measured and simulated data on state-of-the-art SiGe HBTs with a maximum cutoff frequency of approximately 180 GHz. The comparison demonstrates that better accuracy is achieved using this new four-port method. Based on a combination of measurements and HP-ADS simulations, we also show that this new technique can be used to accurately extract the S-parameters and broad-band noise characteristics to frequencies above 100 GHz.