PicoScope 5000D系列:“功能齐全的多面手”

正英国比克公司(Pico Technology)推出Pico Scope5000D系列FlexRes示波器和MSO,其纵向分辨率高达16位,带宽高达200 MHz,采样速率高达1 GS/s。FlexRes硬件在不同时间交织及并行组合中的输入通道上采用多个高分辨率ADC,以优化采样速率,8位ADC分辨率时采样速率可高达1 GS/s,采样率为62.5 MS/s时ADC分辨率可高达16位,或可实现位于二者之间的任意组合。Pico Scope 5000D MSO型号增加了16个数字通道,可为模拟和数字通道提供精确的时间交互关系。可对数     

一种测试高分辨率ADC有效位数的新方法

提出一种测试高分辨率A/D转换器（ADC）有效位数（ENOBs）的正弦拟合法,和传统的正弦拟合法不同,省去了严格选取参数初值的步骤,避免了求解非线性方程组。该方法利用希尔伯特-黄变换（HHT）,从ADC输出数据中逐次拟合出基波曲线和谐波曲线的波形参数,进而求得ENOBs。仿真结果表明,在信号源频率高达1MHz、分辨率分别取7-12位、所含二、三次谐波失真分别为-72dB和-84dB的情况下,运用所述方法实现了对14位ADC的ENOBs的精确评价。     

超低频信号测量中ADC系统的设计与实现

本文分析了超低频交流信号的测量方法,设计了一种基于采样计算方式的ADC采集系统,设计了ADC采样电路及单端转差分驱动电路,分析了ADC量化误差对交流信号测量准确度的影响,提出了交流信号有效值测量准确度与ADC分辨率位数和采样点数的定量关系式。对所设计并实现的ADC采集系统进行了测试,测试数据经线性修正后的相对误差小于等于0.0011%,满足设计目标要求。     

正余弦编码器细分装置的设计

所设计的正余弦编码器细分装置将位置传感器产生的与角度位置成正余弦关系的电信号,采用正切算法计算角度并进行偏差补偿,得到精确的角度位置信号。完成了基于DSP的正余弦编码器角度位置细分装置的软硬件设计,采用全差动放大器件接收差分信号,高速ADC转换芯片+FPGA+DSP实现了区间划分和对信号的细分计算、偏差补偿以及转向判别,使装置具有了信号采集、数据计算和结果输出功能,可用于角度的高分辨率测量。     

泛华恒兴推出带隔离功能的数据采集卡

近日,北京泛华恒兴科技有限公司(简称:泛华恒兴)推出了一款带隔离功能的多功能数据采集卡——PSPXI-3354。PSPXI-3354提供16路信号模拟输入通道,差分8路,内置18位ADC分辨率,单通道采样速率最高位1.25MS/s,多通道共享采样速率最高为1MS/s。4路同步模拟输出,内置16位ADC分辨率,数据更新速率最高位200KS/s。同时,该模块还配有16路数字输入输出端口,2路计数器。     

采用1.75 Gbps串行发送器的低功耗14位125 MSPS ADC

提供了一种适宜于多通道集成的低功耗、小面积14位125 MSPS流水线模数转换器(ADC)。该ADC基于开关电容流水线ADC结构,采用无前端采样保持放大器、4.5位第一级子级电路、电容逐级缩减和电流模串行输出技术设计并实现。各级流水线子级电路中所用运算放大器使用改进的"米勒"补偿技术,在不增加电流的条件下实现了更大带宽,进一步降低了静态功耗;采用1.75 Gbps串行数据发送器,数据输出接口减少到2个。该ADC电路采用0.18μm 1P5M 1.8 V CMOS工艺实现,测试结果表明,该ADC电路在全速采样条件下对于10.1 MHz的输入信号得到的SNR为72.5 d BFS,SFDR为83.1 d B,功耗为241 m W,面积为1.3 mm×4 mm。     

一种新颖的绝对式磁栅位移传感器

为了提高磁栅的分辨率,降低成本并实现绝对式输出,构建了一种磁栅结构。采用永磁体作为磁栅源,6个气隙为2.8mm的线性霍尔把磁信号转换成电信号,经过差分得到三相电压信号,在信号处理上采用基于校准查表的信号处理方式。在离线状态下,用高分辨率的光栅对磁栅进行校准。对光栅的输出和磁栅的三相信号同时采样并上传到计算机,得到标准位移和三相信号的对应关系并存储在主控芯片中以供查表。实际工作状态中,分区间根据三相信号查表得到位移。根据此原理制出样机,实现了单信号周期内的绝对位置检测,分辨率达到0.001mm以下,结构简单、成本低廉。     

多通道能谱分析系统的通道复用技术

能谱分析是一种重要的核辐射分析方法,探测器将接收到的核辐射脉冲转化为电信号,经电路整形后送入ADC进行数模转换,然后再经处理器处理得到能谱数据。ADC采样率和采样位数越大,测得的核脉冲信号就越准确,系统的能量分辨率就越高。而高采样率与采样位数往往不可兼得,为了提高能谱分析系统采样率,提出采用通道复用技术让多个16位ADC并行采样以提高采样率。使用NI公司的8通道USB‐7845R数据采集卡,将两个采样率为500 k／s的ADC复用得到1 M／s的采样率,构建了4通道的能谱分析系统,验证了通道复用技术的可行性和稳定性。实验结果表明,多通道复用技术可以在不改变硬件电路的情况下提高能谱分析系统的采样率,从而提高能量分辨率。     

基于峰差法的磁通门磁探仪的研制

研究了一种基于峰差法的磁通门磁探仪系统。该系统由A Tmega8L单片机产生数字方波激励信号直接驱动磁通门探头,改善了传统RC模拟激磁电路的稳定性问题;用结构更加简单的峰值检波电路取代传统复杂的谐波法电路,简化了电路设计,并降低了系统功耗;采用16位专用ADC对磁通门输出信号进行采样,保证了系统的分辨率;为进一步控制系统温漂,增加了温度检测补偿模块。实验结果表明,该系统实现了预期功能,性价比较高,具有良好的推广价值。     

流水线模数转换器设计

设计了一款14位、125MS/s流水线模数转换器(ADC)。通过前端采样/保持电路(SHA)消除对输入信号采样的孔径误差,采用4位结构的首级转换电路提高ADC线性性能,设计了带输入缓冲的栅压自举开关以缓解首级转换电路输入采样开关中自举电容对SHA的负载效应,流水线ADC级间通过逐级按比例缩减策略使功耗得到节省。该设计采用0.18μm 1P5MCMOS工艺,ADC版图面积2.3 mm×1.4 mm。Spectre后仿真结果显示,采样频率125 MHz、输入信号在接近Nyquist频率(61MHz)处时信号噪声畸变比(SNDR)和无杂散动态范围(SFDR)可分别达到75.7 dB和85.9 dB。在1.8V电源电压下,ADC核心部分功耗为263 mW。     

双通道雷达数据采集系统的设计与实现

针对雷达信号处理领域需要将雷达回波模拟信号数字化的需求,本文采用A/D专用芯片并行采样、FIFO数据缓存和FPGA时序控制的方法,设计并实现了一种双通道雷达数据采集系统,采样频率为220 MHz.系统实现简单,工作稳定.对系统进行的性能测试表明,I、Q双通道采集到的信号相位一致性能较好,A/D有效位数为6位以上,满足实际应用的需要,适用于高速数字信号处理领域.     

Four innovative calibration algorithms for capacitive mismatch in 18-bit redundant split SAR ADC

Four calibration algorithms based on the order statistics about capacitive mismatch are proposed for successive approximation register (SAR) analog-to-digital converter (ADC). An 18-bit split capacitive SAR ADC architecture with redundant bits was used to verify the four calibration algorithms proposed. The main dynamic parameters of the SAR ADC were simulated in MATLAB by 500 Monte-Carlo runs with a standard deviation of 0.1% (σ₀/C₀ = 0.001 ). And the simulation results of sorting and regrouping method II (SRGII) show that a 21.64-dB enhancement of spurious-free dynamic range (SFDR) and a 3.33-bit improvement of effective number of bits (ENOB) have achieved respectively, whereas the simulation results of sorting and re-exchanging method I (SREI) show that a 21.64-dB enhancement of SFDR and a 3.34-bit improvement of ENOB have achieved, respectively     

基于编码器测速的双闭环控制系统性能分析

为了探究编码器测速对闭环控制系统的影响,更好的利用编码器提高测速和控制效果,首先说明了编码器测速原理,然后分析了差分速度估计法中编码器自身分辨率和采样周期对速度估计的影响,其后对闭环控制系统进行了分析,得出在速度带宽一定的情况下,编码器的采样频率变化对位置信号测量没有影响;而在满足系统带宽的情况下,编码器的采样频率越大,对速度测量造成的误差越大,最后用实验验证编码器采样频率变化对整个闭环控制系统的影响。     

几种利用ADC采样测量时钟抖动方法的比较

研究了使用ADC采样测量时钟抖动的基本原理,在阐述了已经公开发表的利用ADC采样测量时钟抖动的“相干测量法”和“信噪比测量法”的基本思想之后,本文还给出了一种基于正弦信号四参数估计测量时钟抖动的“参数估计法”,同时通过MATLAB仿真比较了这几种方法的优劣。仿真结果表明,“参数估计法”在这几种方法中具有独特的优势。总的来说,利用ADC测量时钟抖动的大小和分布具有测量设备简单,测量方法简便、快捷,测量结果精度高等特点。     

基于查表原理的单对磁极编码器研制

与光电编码器相比,磁性编码器结构简单、易微型化、且不受尘埃及结雾的影响,但其分辨率和精度较低且难以提高,严重制约了其应用和发展。针对单对磁极编码器,深入分析了传统处理方式上存在的缺陷,提出一种基于标定查表的信号处理方式。采用六路霍尔传感器均布在圆周上,把变化的磁场转换成电压信号,经差分得到查表用三相电压信号。在离线状态下,用高精度光电编码器对电压信号与电机旋转角度进行标定,并把角度数据存储在EEPROM中。工作过程中采用三相电压信号分区间查表得到电机旋转角度值,用FPGA(programmablegatearrayField)进行信号处理,实现了分辨率15位,精度14位(16384线)的角度输出,能够满足电机恶劣环境下高精度位置检测的要求。     

A 15-MHz bandwidth double sampling MASH25b-15b sigma-delta modulator with DEM for multibit DACs

A high SNDR discrete-time (DT) 2-1 MASH sigma-delta modulator (SDM) for 15-MHz bandwidth was presented. Cascade of integrators with feedforward (CIFF) scheme, combined with the optimized gain coefficients, was adopted to avoid of the integrators. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. Five-bit flash quantizer was adopted in both stages to improve the overall signal-to-noise and distortion ratio (SNDR) performance, and third-order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated in a mature 0.18-μm CMOS technology, the occupied area of the modulator was 0.24 mm² and dissipation power 25.4 mW from a 1.8-V voltage supply. As a sampling rate of 240 MHz for the input sampling and DAC and 480 MHz for the flash ADC, a SNDR of 90.2 dB over 15-MHz signal bandwidth and the corresponding effective number of bits (ENOB) of 14.69 bit were achieved. The spurious-free dynamic range (SFDR) was 98 dB with DEM turned on for a 3.75 MHz at −2.5-dBFS input signal, and the figure of merit (FOM) was 30.7 fJ/conv. for 15-MHz bandwidth. A 15-MHz bandwidth multibit MASH2-1 discrete-time sigma-delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. High-order DEM was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18-μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15-MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high-frequency biomedical imaging or sensing systems, and so on.     

磁旋转编码器在永磁同步电机位置测量中的应用

为了检测永磁同步电机磁极位置,在电机位置传感器安装之后要对其进行初始定位.根据电机反电动势信号与电机位置角的关系,利用电机反电动势过零信号来定位磁旋转编码器.根据这一方案,无需调整编码器的安装位置即能够确定磁旋转编码器所输出的绝对角度与电机位置角的关系.测试结果还表明,根据磁旋转编码器输出的绝对角度,在电机刚开始转动时就能够精确检测出电机磁极的初始位置,其分辨率能够满足课题要求.     

Flexible fingerprint sensor driver IC and bendable evaluation

The paper presents a flexible polyimide fingerprint sensor driver IC driven by a 0.18-μm CMOS technology and studies the sensor bendable performance. The finger valley and ridge are sensitive to environment noise; therefore, we propose low-ripple cross non-overlap charge pump that performs 7.2 V pumped output voltage with Δ30 mV ripple and 98.36% pump efficiency to increase the sensing level and propose mutual V_ref SAR ADC circuit with 6.6 V input swing range, 30 MS/s, ENOB of 10 bits, SNDR 74.1 dB, and bit error with INL [0.61, −0.7] and DNL [0.9, −0.62] to enhance the resolution. Through low-ripple charge pump and mutual V_ref SAR ADC circuitry implementation, it makes the sensing of fingerprint valley and ridge capacitance signal still distinguishable when the film is bent harshly by the substrate radius 10 mm and, in the meanwhile, meet the FBI PIV biometric fingerprint image quality, which is upmost tough standard in biometric fingerprint of identification product.     

A charge-sharing analog-to-digital converter with embedded downconversion using a variable reference voltage

In the field of radio receivers, downconversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the converter's performance in terms of noise and linearity. As an alternative, we propose a receiver architecture that considers the ADC as both a quantizer and a downconverter block. This is achieved through the use of a variable reference signal (in this case, a voltage), as opposed to classic time-invariant reference signals. When embedded into a charge-sharing (CS) successive approximation register (SAR) ADC, this varying reference voltage is “saved” in the digital-to-analog converter (DAC) capacitor bank during the sampling phase, preventing any conversion errors. Furthermore, a phase-locked loop (PLL) is used in order to provide an on-chip solution for the generation of this variable reference voltage, which also removes the need for dedicated bandgap circuits and reference buffers. Post-layout simulations of an 8-bit 50 MS/s CS-SAR ADC show that the proposed “embedded mixing” technique is able to downconvert a high-frequency signal while also increasing the effective resolution by around 0.5 bits, when compared with a standard DC reference voltage.