一种高速自控预充电灵敏放大器的设计

提出了一种用于非挥发性存储器的新型电压灵敏放大器.该电路采用一种可以自动关断、电流可控的预充电路,可以有效消除由于存储容量变大带来的巨大位线寄生电容的影响,有效提高了灵敏放大器的读取速度.经验证,该结构具有较快的读取速度,在3.3 V工作电压下,电路读取时间为11 ns.     

OTP存储器位线负载对读出速度的影响

在OTP存储器设计中,随着存储器容量的不断加大,位线负载也相应变大,可能导致读机制失效。为了防止发生读机制失效,需增加灵敏放大器充电时间,但是延长充电时间会影响读取速度。在分析OTP存储器灵敏放大器工作原理的基础上,重点研究了位线负载对读出速度的影响。通过仿真,优化了OTP存储器的读出电路参数。     

一种新型高速度低功耗灵敏放大器的设计

在存储器件容量不断增大的过程中．巨大的位线寄生电容越来越严重的影响着它的电学性能。本文介绍了一种新型高速低功耗灵敏放大器的设计方法,此种灵敏放大器具有自控预充电的特点。采用该放大器的Flash Memory有较高的数据读取速度和准确性,电学性能优良。     

表面电荷器件的RAM存储器

以前,电荷转移器件只能制作移位寄存器,现在美国通用电气公司使用表面电荷晶体管制成了动态随机存取存储器(RAM)。这存储器为4×8位阵列,可发展为4096位存储器。每位面积为2.5密耳~2,存取时间150毫微秒,循环时间250毫微秒。制造存储器采用耐熔金属MOS工艺,其目的是使其单元结构能与当前MOS RAM的单晶体管结构同样简单,单晶体管单元存在的问题是位线的电容很高,往往导致逻辑信号电平的损耗。为解决这问题,GE公司先将电荷从位线存储区取出,然后从位线转移到     

基于位线循环充电SRAM模式的自定时电路设计

随着集成电路的密度和工作频率按照摩尔定律所描述的那样持续增长,使得高性能和低功耗设计已成为芯片设计的主流。在微处理器和SoC中,存储器占据了大部分的芯片面积,而且还有持续增加的趋势。这使存储器中的字线长度和位线长度不断增加,增加了延时和功耗。因此,研究高速低功耗存储器的设计技术对集成电路的发展具有重要意义。对SRAM存储器的低功耗设计技术进行研究,在多级位线位SRAM结构及工作原理基础上,以改善SRAM速度和功耗特性为目的,设计了基于位线循环充电结构的双模式自定时SRAM,其容量为8K×32 b。     

部分耗尽SOI静态存储器位线电路的研究

对部分耗尽SOI CMOS静态存储器的位线电路进行了模拟和研究,详细分析了BJT效应对SRAM写操作过程的影响,给出了BJT效应在SRAM写操作过程的最坏条件和最好条件下存储单元门管的瞬态泄漏电流的模拟结果;在详细分析BJT效应影响的基础上,对"First Cycle"效应进行了全面的研究.结果表明,"First Cycle"效应对写操作影响较大;研究了位线电容负载对存储单元门管体电位的依赖.最后,给出了研究结果.     

一种4-Mb高速低功耗CMOS SRAM的设计

高性能的系统芯片对数据存取速度有了更严格的要求,同时低功耗设计已成为VLSI的研究热点和挑战.本文设计了一款4-Mb(512K×8bit)的高速、低功耗静态存储器(SRAM).它采用0.25μm CMOS标准工艺和传统的六管单元.文章分析了影响存储器速度和功耗的原因,重点讨论了存储器的总体结构、灵敏放大器及位线电路.通过系统优化,达到15ns的存取时间.     

语音合成集成电路中掩模ROM的解决方案

在语音合成集成电路(IC)中,需要存储大量的程序和语音数据,因此内存储器的集成度、读取速度及可靠性成为影响一款芯片生产成本和性能参数的关键指标。存储器有很多分类,掩模只读存储器(ROM)以其较高的集成度和较低的成本在中低档消费类语音合成IC中有着较为广泛的应用。给出一种语音合成IC中掩模ROM的解决方案,分别介绍3个组成部分:存储单元阵列、地址译码器和读出放大器的设计实现。采用该方案可以有效提高掩模ROM的集成度、读取速度及可靠性,有效降低语音合成IC的生产成本、提高其性能和市场竞争力。     

一种高速MaskROM的设计研究

文章分析讨论了掩模只读存储器的工作原理和结构,并结合实际工作,详细论述了一个高速的576k位MaskROM的设计与实现.针对字线负载大、速度慢的问题,从选择合适的译码方案和减少字线上RC负载两个方面,提高字线的响应速度,从而使MaskROM的读取时间有较大提高.该款MaskROM采用0.5μm CMOS工艺,电源电压5...     

高兼容CMOS工艺嵌入EEPROM技术

电可擦除只读存储器是非易失性存储器。文章介绍了高兼容常规CMOS工艺的一种嵌入式电可擦除只读存储器设计与工艺技术,对电可擦除只读存储器单元、高压MOS器件的结构与技术进行了研究。研究结果表明,我们设计的0．8μm电可擦除只读存储器单元Vpp电压在13V～15V之间能够正常工作,擦写时间小于500μs,读出电流大于160μA／μm;在普通CMOS工艺基础上增加了BN＋埋层、隧道窗口工艺,成功应用于含嵌入电可擦除只读存储器的可编程电路的设计与制造。     

A 65 mW 128K EB-ROM

A low power read-only memory (128K EB-ROM) has been developed using direct electron-beam data writing and 2 /spl mu/m VLSI fabrication technology. Programming of information in the ROM is accomplished by selective use of a field oxide in place of a thin gate oxide. The memory cell array is divided into eight current discharge (CD) units. Only one of the eight CD units, which contains a selected cell, is activated by the 3-bit extra decoder. The large capacitance enlarged by the Miller effect is markedly reduced. Moreover, the total capacitance to be precharged is also reduced. High performance output buffer circuitry is adopted, which has a high logic threshold voltage. As a result, the fabricated 128K EB-ROM is capable of 65 mW power dissipation under 400 ns cycle time and 5 V DC supply voltage conditions and 200 ns access time. Memory cell and chip dimensions are 8 /spl mu/m/spl times/7.75/spl mu/m and 3.75 mm/spl times/5.5 mm, respectively.     

Minimum size ROM structure compatible with silicon-gate E/D MOS LSI

Describes a new read-only memory (ROM) with minimum geometry. A cascade ratioless circuit configuration is used, which is process compatible with silicon-gate metal-oxide semiconductor (MOS) large-scale integration (LSI) using depletion load MOSTs. The content of a memory cell in the new ROM is determined by the choice of the MOST threshold mode, either an enhancement or depletion mode; this differs from the conventional ROM structure where the content of a memory cell is distinguished by the thickness of gate oxide. The size of a single bit of the ROM is only 196 /spl mu/m/SUP 2/ and is a reduction of 45 percent compared to a conventional silicon-gate ROM.     

A 1-GHz logic circuit family with sense amplifiers

This paper describes a newly developed logic circuit family based on dual-rail bit lines and sense amplifiers that is used extensively in a 1.0-GHz, single-issue, 64-bit PowerPC integer processor, gigahertz unit test site (guTS). The family consists of an incrementor, a count-leading-zero, a rotator, and a read-only memory. Each macro consists of a leaf-cell array, dual-rail bit lines, a row of sense amplifiers, a control block, and peripheral circuits. A common read-out scheme sensing the differential voltage of dual-rail bit lines is used. The hardware was fabricated in a 0.25-μm drawn channel length, six-metal-layer (Al) CMOS technology (1.8-V nominal VDD). Wafer testing was performed using a probe card. The macros were tested cycle by cycle by scanning the input data to the read/write address latches and data latches, and scanning the result out from the output receiving latches. Functional testing was performed on guTS macros at frequencies up to 1.0 GHz at 25°C with nominal VDD (1.1 GHz for the ROM)     

All-optical erasable programmable read-only memory (EPROM) based onLiNbO3 channel waveguides

The erasable programmable read-only memory (EPROM) consists of three channel waveguides. Two are made by the proton-exchange technique to construct a directional coupler as the read-in and read-out units. The third, placed in between the other two, is made by the Ti-indiffusion technique to function as the memory storage unit as well as the control channel. The operation principle is based on the combination of the directional coupler switch and the photorefractive effect. The EPROM also operates as an all-optical switch if a short-pulsed laser with high-energy density is used to write and erase, and the speed should be on the nanosecond time scale or even faster. Theoretical calculation of some typical designs shows that very small light energy (0.06-0.6 mJ) is needed for the device operation     

A low-power ROM using single charge-sharing capacitor and hierarchical bit line

This paper describes a low-power read-only memory (ROM) using a single charge-sharing capacitor (SCSC) and hierarchical bit line (HBL). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a minimal voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and to make it easier to design. Furthermore, the HBL saves power by reducing the capacitance and leakage current in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with 4 K/spl times/32 bits consumes only 37% power of a conventional ROM. An SCSC-ROM chip is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 8.2 mW at 240 MHz with 2.5 V.     

一种OTP存储器高速读出机制的设计

本文设计了一种用于OTP存储器的高速读出机制.该读出机制由内部电路产生读控制时序,采用地址变化探测电路、脉冲宽度调整及控制信号产生电路、采样与锁存电路来实现读取操作.其具有电路结构简单,读出速度快,读出准确,抗噪声、抗干扰能力强,功耗低的特点.仿真结果表明整个读取周期仅为24ns,数据口的读出信号稳定准确,不会产生读取误操作.     

Stable fully-printed polymer resistive read-only memory and its operation in mobile readout system

The read-only memory (ROM) is a key component for a wide range of printed electronics applications. The resistive type ROM based on conductive polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonate) (PEDOT: PSS) would be a promising technology of choice, which can be “manufactured-on-demand” via digital printing for high throughput and material saving. However, the instability issues associated with the conventional PEDOT: PSS and its interface with contact electrodes would be a critical hurdle preventing the technology from practical applications. This work proves that, by removing the hydrophilic acidic groups in conventional PEDOT: PSS, these instability issues can be well addressed. The ROM tags fabricated based on the modified PEDOT: PSS of neutral pH and inkjet printed silver electrodes present extremely stable performance under both aging and electrical stress tests in air ambient. A self-designed memory readout circuit board, communicating with mobile phone through near field communication, is also implemented to demonstrate the feasibility of using the ROM tags in real mobile systems. It is shown that, without any encapsulation, the ROMs can have stable output under high humidity condition (>60% RH), after either being stored in the ambient condition for 30 days or being operated after 20000 reading cycles.     

ROMHD and ROMLD

An embedded read-only memory architecture with a complementary cell and two interchangeable power/performance design points is described. This article focuses on the novel features of 0.13-/spl mu/m embedded, compilable read-only memory (ROM). A complementary array cell that increases and maintains signal margins across array sizes despite the ever-increasing capacitive coupling effects and lower voltages of each succeeding technology generation is described here along with a new architecture that allows a customer to switch between two different power/performance design points while only changing the metal wiring in the ROM via a compiler. Hardware data is presented that illustrates the success of the array design and the difference between the two power/performance design points.     

A giant chip multigate transistor ROM circuit design

Defect-tolerant techniques based on memory-cell duplication with address dispersion, fail-safe operation, and defect-tolerable combination decoding were developed to improve the fabrication yield of a large-chip-size mask-programmable read-only memory (ROM). These techniques have features of automatic inspection, detection, and selection. A multigate transistor ROM (MUGROM) cell and a high-sensitivity charge-transfer sense amplifier appropriate to this MUGROM have been developed which achieve high packing density and low power dissipation. Using these techniques and n-well CMOS technology, a 4-Mb ROM with an internal I/O port on a 34/spl times/21-mm/SUP 2/ size chip has been realized. It enables the ROM to be connected to the microprocessor data bus without peripheral interface LSI. The I/O port was designed to have two READ modes: a block data access mode for reading continuous data up to 1-kbit with fast cycle time, and a random access mode. Operating under a 1-MHz block data READ cycle, the device has a typical power dissipation of 20 mW with an access time of 7 /spl mu/s.