一种面向CMP的可变相联度混合Cache结构

以V-Way Cache结构为原型,提出一种面向CMP的可变相联度混合Cache结构CMP-VH.CMP-VH将最后一级片上Cache划分成一种优化的私有/共享结构,Tag私有,数据部分私有部分共享.采用基于数据块的重用信息替换策略,提供显式和隐式两种机制在核间对共享数据进行容量划分.并行程序负载SPLASH-2的模拟...     

一种基于伪LRU的新型共享Cache划分机制

本文提出了一种基于伪LRU方法的新型共享Cache动态划分策略PLRU-SCP.本文提出的划分策略在分析电路中给出了基于二叉树的新型分析方法,在划分电路中使用了一种非遍历的划分算法.并提出了一种新型共享Cache结构.本文提出的新型划分策略比基于LRU方法的不划分共享Cache策略和效用最优的划分策略的性能分别提高了11.05%和8.66%.     

一种基于频率的多核共享Cache替换算法

LRU替换算法在单核处理器中得到了广泛应用,而多核环境大都采用多核共享最后一级Cache(LLC)的策略,随着LLC容量和相联度的增加以及多核应用的工作集增大,LRU替换算法和理论最优替换算法之间的差距越来越大。该文提出了一种平均划分下基于频率的多核共享Cache替换算法(ALRU-F)。该算法将当前所需要的部分工作集保留在Cache内,逐出无用块,同时还提出了块粒度动态划分下基于频率的替换算法(BLRU-F)。该文提出的ALRU-F算法相比传统的LRU算法缺失率降低了26.59%, CPU每一时钟周期内所执行的指令数IPC(Instruction Per Clock)则提升了13.59%。在此基础上提出的块粒度动态划分下,基于频率的BLUR-F算法相比较传统的LRU算法性能提高更大,缺失率降低了33.72%,而IPC 则提升了16.59%。提出的两种算法在性能提升的同时,并没有明显地增加能耗。     

多核实时线程间干扰分析及WCET估值

在共享Cache的多核处理器中,线程在共享Cache中的指令可能被其他并行线程的指令替换,从而导致了线程间在共享Cache上的干扰.多核结构下WCET估值需要考虑并行线程间在共享Cache上的干扰.针对当前典型的共享Cache和共享总线的多核结构,本文提出了一种迭代的WCET估值分析方法.考虑共享总线对共享Cache访问的时序影响,基于该时序分析线程间在共享Cache上的干扰,得到较精确的WCET估值.理论分析证明了该方法的有效性,实验结果表明本文的分析方法较之当前的两种方法分别可以提高21%和14%的精确度.     

多核中Cache管理策略分析

本文首先分析了多核系统中二级Cache私有和共享管理方式的优缺点.并在此基础上,分析了现有的基于私有和共享方式的优化策略,现有的优化策略均通过混合私有和共享的方式在Cache访问延迟和Cache命中率之间找到一种平衡.     

CCSim：基于Pin的CMPCache访问模拟器

随着芯片集成制造工艺的日益发展,拥有多级Cache的片上多处理器(CMP)已成为桌面应用和高端计算的主流平台.为了优化程序在CMP下运行性能,文中以Pin工具软件为基础,提出并设计了一个面向CMP体系架构的多级Cache访问模拟器——CCSim.该模拟器不仅可以模拟同构CMP下传统方式的Cache访问,而且还可以对CMP中最后一级共享Cache的竞争访问以及非传统方式的Barcelona式Cache访问模式进行模拟分析.     

一种DSP指令Cache的功耗优化策略

高性能DSP器件对功耗指标要求越来越高,功耗主要来源于对存储空间的访问,因此提出了一种改进型Cache功耗优化策略,实现了对指令Cache的分阶段访问,同时兼顾了Cache的动态功耗和静态漏流功耗的优化,改进了传统的基于非分阶段访问的按需唤醒策略NPOWP(Non-Phased Cache with On-Demand Wakeup Prediction)显著影响处理器性能的缺点。设计应用于DSP设计的4路组相连昏睡指令Cache中,使用基于分阶段访问的按需唤醒策略POWP(Phased Cache with On-Demand Wakeup Prediction)策略平均可降低75.4%的指令Cache功耗,降低6.7%的处理器总功耗,性能损失仅为0.77%.     

一种结合动态写策略的磁盘Cache替换算法

磁盘Cache是改善I/O性能的一种技术.通过分析Cache写策略和LRU、LFU替换算法对磁盘Cache性能的影响,引入一种动态写策略,改进替换算法,使基于频率的块替换算法FBR与动态写策略相结合.二者结合较好地应用于磁盘存取中,充分利用局部性规律,提高I/O性能,使磁盘在多种工作环境和不同Cache大小下的性能更优.     

针对SMS4密码算法的Cache计时攻击

分别提出并讨论了针对SMS4加密前4轮和最后4轮的访问驱动Cache计时分析方法,设计间谍进程在不干扰SMS4加密前提下采集加密前4轮和最后4轮查表不可能访问Cache组集合信息并转化为索引值,然后结合明文或密文对密钥的不可能值进行排除分析,最终恢复SMS4初始密钥.实验结果表明多进程共享Cache存储器空间方式和SMS4查找表结构决定其易遭受Cache计时攻击威胁,前4轮和最后4轮攻击均在80个样本左右恢复128bit SMS4完整密钥,应采取一定的措施防御该类攻击.     

多核处理器预取策略的研究

多核处理器的内存和Cache共享策略使内存访问延迟成为影响多核处理器性能的瓶颈,预取技术能够隐藏访问延迟,对提高多核处理器的性能有重要意义.分析并比较了一系列典型的预取策略,讨论了它们的优缺点,对几种新颖的基于硬件的多核预取技术提出了改进方案,讨论了在多核处理器体系结构下,预取策略面临的挑战和必须考虑的设计问题,为多核预取提供了创新的思路.     

SRCP: sharing and reuse-aware replacement policy for the partitioned cache in multicore systems

Although multi-core processors enhance the performance yet the challenge of estimating Worst-Case Execution Time (WCET) of a task remains in such systems due to interference in shared resources like Last Level Caches (LLC). Cache partitioning has been used to reduce the interference problem by isolating the shared cache among each thread to ease the WCET estimation. However, it prevents information shared among parallel threads running in different cores. In current work, we propose sharing and reuse aware partitioned cache (SRCP) framework such that replication of shared information, data, or instruction, in different partitions could be avoided in LLC. Further, enhancement in existing cache replacement policy is proposed, which avoids eviction of cache blocks shared among multiple cores accessing partitioned last level cache. Tighter WCET, as well as improved resource utilization, is thereby ensured with the proposed framework. Experimental results show that SRCP shows significant improvement in cache hit-rate for PARSEC and SPLASH2 benchmarks as compared to least recently used cache replacement policy and outperforms EHC and TA-DRRIP, which are state-of-the-art replacement policies.

     

数据网格中一种填空式副本分配算法

在数据网格应用中,数据会由于性能和可用性等原因进行复制.如何使数据复本合理分布以降低通信开销是数据网格系统需要解决的重要问题.本文针对一种简化的数据网格环境,考虑存储资源代理对数据的访问频率和代理间的网络性能,提出一种填空式数据副本分配算法(CDRDA).通过该算法得到的数据副本分配,构成多级虚拟存储架构.数据副本根据被存储资源代理访问的频率分布在访问开销小的节点上,从而使系统的整体访问效率达到近似最优.     

A 45 nm 8-Core Enterprise Xeon¯ Processor

This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon^? EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the unterminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.     

同时多线程D-cache的分配与安全

D—cache是同时多线程处理器的重要共享资源，其分配方式不但影响处理器性能，而且关系到各线程的数据安全。文章提出D—cache按路动态分配策略，其特点如下：消除各线程间的cache替换冲突，彻底消除隐蔽信道的风险：根据各线程的运行情况动态调整D—cache分配，提高资源利用率；实现代价低。     

面向非规则大数据分析应用的多核帮助线程预取方法

大数据分析应用往往采用基于大型稀疏图的遍历算法,其主要特点是非规则数据密集访存。以频繁使用的具有大型稀疏图遍历特征的介度中心算法为例,提出一种基于帮助线程的多参数预取控制模型和参数优化方法,从而达到提高非规则数据密集程序性能的目的。在商用多核平台Q6600和I7上运用该方法后,介度中心算法在不同规模输入下平均性能加速比分别为1.20和1.11。实验结果表明,帮助线程预取能够有效提升该类非规则应用程序的性能。     

Improving Java performance and energy dissipation through efficient code caching

Traditional Java code generation and instruction fetch path is not efficient, as Java binary code is typically written into the data cache first, and then is loaded into the instruction cache through the shared L2 cache or memory, which takes both time and energy. In this paper, we study three hardware-based code caching strategies, which attempt to write and read the dynamically generated Java code faster and more energy-efficiently. Our experimental results indicate that with proper architectural support, writing code directly into the instruction cache can improve the performance for a variety of Java applications by 9.6% on average, with up to 42.9%. Also, the average energy dissipation of these Java programs can be reduced by 6% with efficient code caching.     

Selective Data Deactivation Mechanism in Sustainable Area-based Cache for Mobile Social Networks

This paper presents a proposal of a more resilient mechanism of an area-based sustainable cache system under a temporary decrease of the number of terminals. This mechanism suppresses interruptions of data relay and disappearances of cache data in the cache continually. The core technology enables each terminal to retain the received data in cache areas as ??deactivated data?? instead of deleting the data, even after a terminal leaves the area. Deactivated data are not relayed outside the target designated cache area. The data are reactivated and redistributed to others as relay data once the terminal revisits there. Consequently, the data are shared across time. Furthermore, particularly addressing the limitation of terminal storage, we proposed an adaptive scheme to select which data should be retained as deactivation data. This new mechanism leverages the proposed method under the storage limitation. As presented at the end of this paper, the simulation evaluations underscore the effectiveness of the proposed mechanism, and the adaptive selective scheme of deactivated data.