Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die

The cost and quality of a multichip assembly is highly dependentupon the cost and quality of the incoming die. In the case of a baredie assembly, it is often highly desirable to use either Known Good Die(KGD) or die that have been burned-in and tested to the same level ofquality and reliability as their packaged die equivalents. However,performing full bare die burn-in and test may not always becost-effective. This paper examines the question of whether it isalways necessary to use KGD to produce a cost-effective multichipmodule (MCM) of acceptable quality. A process-flow based cost modelis used to compare the cost and quality of MCMs assembled with KGD toMCMs assembled with die that have received wafer-level test only. Inaddition to test effectiveness at the wafer, die, and module level,factors that are considered include die complexity (size and I/O), number of die per MCM, the cost of producing the KGD, andrework costs and effectiveness. The cost model captures inputs fromwafer fabrication through MCM assembly and rework. Monte Carlosimulation is used to account for uncertainty in the input data.The resulting sensitivity analyses give final MCM cost and quality asa function of the various factors for both KGD and die that havereceived wafer-level test only.     

多芯片组件的检测方法

多芯片组件的测试分三类：基板、ＩＣ裸芯片和组件测试。各类测试都有若干种不同的测试方法，如多层基板的电学测试法，光学测试法；ＩＣ裸芯片的内建自测试法，界面扫描法；组件的全功能测试法，有限功能测试法等。本文对这些方法的优点与不足处，测试设备使用时应注意的事项，适用对象等作了详尽的介绍，还对各种类似方法的功能作了比较。     

裸芯片封装技术的发展与挑战

随着IC制造技术的发展,传统的封装形式已经不能够满足集成电路对于高性能、高集成度、高可靠性的要求。裸芯片由于其本身具有的特点而被广泛应用于HIC/MCM等新型的封装形式中。文章的目的在于分析使用裸芯片所带来的技术优势和存在的一些不足之处,使得人们能够更加客观地看待一种新的技术,并且扬长避短地利用好它。一方面裸芯片的引入能够提高系统集成度和速度,这是裸芯片应用技术发展的必然性;另一方面针对裸芯片应用技术存在的问题,文章着重介绍了两种解决方法,即通过发展KGD技术和改进工艺的方法来提高裸芯片的质量和可靠性。     

Self-Timed Boundary-Scan Cells for Multi-Chip Module Test

This paper presents a self-timed scan-path architecture, to be used in a conventional synchronous environment, and with basic application in digital testing and interconnections checking in a Smart-Substrate MCM (T.A. García, A.J. Acosta, J.M. Mora, J. Ramos, and J.L. Huertas, Self-Timed Boundary-Scan Cells for Multi-Chip Module Test, Proceedings of IEEE VLSI Test Symposium, April 1998, pp. 92–97). With this approach, the potential advantages of self-timed asynchronous systems are explored for their practical use in a classical MCM testing application. Three different self-timed asynchronous boundary scan cells are proposed (Sense, Drive and Drive & Sense cells) that can be connected to form a self-timed scan-path. The main advantage is that no global test clock is needed, avoiding clock skew and synchronization faults in test mode, and hence, a more reliable test process is achieved. These cells have been designed and integrated in active substrates, building several boundary-scan configurations and being fully compatible with the ANSI/IEEE 1149.1 Standard. The experimental results, as well as their comparison with their synchronous counterparts, show the feasibility of the proposed self-timed approach for testing interconnections in a MCM.     

Known Good Die

Advances in reducing size and increasing functionality of electronics have been due primarily to the shrinking geometries and increasing performance of integrated circuit technologies. Recently, development efforts aimed at reducing size and increasingfunctionality have focused on the first level of the electronicpackage. The result has been the development of multichip packaging,technologies in which bare IC chips are mounted on a single high density substrate that serves to package thechips, as well as interconnect them. A number of benefits accruebecause of multichip packaging, namely, increased chip density,space savings, higher performance, and less weight. Therefore, thesetechnologies are attractive for today's light weight, portable, highperformance electronic equipment and devices.In spite of these benefits, multichip packaging has not shown the kind of explosive growth and expansion that was predicted[1]. A major inhibitor for these technologies has been theavailability of fully tested and conditioned bare die, orknown good die. This paper reviews the issues and technologies associated with test and burn-in of bareor minimally packaged IC products.     

Smart Substrate MCMs

This paper presents a cost-based assessment of the effectiveness of Smart Substrate MCM Systems. A Smart Substrate MCM System is one in which the substrate contains active circuitry for carrying out testing functions. The feasibility of using this approach is investigated. The Smart Substrate strategy is compared to an alternative approach based on the assumption that system components are perfect (Known Good Die (KGD) approach). The obtained results identify the domain of applicability of Smart substrate MCMs and point to limitations of the KGD approach.     

Current Testing Procedure for Deep Submicron Devices

This paper presents a test technique that employs two different supply voltages for the same IDDQ pattern. The results of the two measurements are subtracted in order to eliminate the inherent sub-threshold leakage. Summary of the experiment carried out on System on a Chip (SOC) device build in 0.35 technology is also shown. These experiments proved that the method is effective in detecting failures not detectable with the single limit IDDQ.     

CMOS Differential and Absolute Thermal Sensors

This paper treats the test of CMOS digital ICs by using the thermal mapping of the silicon surface as a test observable. Two different temperature-sensing strategies are presented. The novel sensors developed are an on-chip CMOS Differential Temperature (DT) sensor and a Proportional to Absolute Temperature (PTAT) sensor. The sensors have been implemented in a standard .18 m CMOS technology.     

Year 2000 — a Sytems Integration challenge

BT, along with virtually every other IT-dependent business worldwide, is tackling a problem which is quite unique and if not corrected could be disastrous. The problem, sometimes known as the Year 2000 bug or millennium time bomb, has been caused by the use of two digits to represent the year in the majority of our systems and applications. The problem is technically not difficult to fix but the volume of changes occurring, and the need to potentially test every system to ensure that it is year 2000 proof, presents unique and challenging difficulties for integration and testing. Why this is the case, what problems need to be addressed, and an overview of some of the proposed integration and test strategies to tackle these problems, is the subject of this paper.     

星载高可靠裸芯片设计*

通过研究裸芯片的可靠性保证技术,提出了集成的已知良好芯片(KGD鄄确优裸片)的可靠性保证指南,并制定了完善的裸芯片设计、生产、过程控制和可靠性评估等技术流程。文章确定了KGD 的规范线,作为裸芯片可靠性测试的检验标准。根据KGD 规范线对裸芯片进行全频测试,并进行3MHz 老化试验。通过试验,可以确保KGD 的可靠性指标达到IC 封装的要求,最终实现使用裸芯片的星载电子装备小型化、轻量化、高可靠、多功能和低成本。     

An Inductorless 300 MHz Wideband CMOS Power Amplifier

The power amplifier tends to be one of the most demanding parts to fully integrate when building an entire radio on a CMOS chip. In this paper the design of a fully integrated RF power amplifier without inductors is described. As inductors in CMOS technology are associated with various problems, it is interesting to examine what performance can be achieved without them. An amplifier with an operating band from 60 MHz to 300 MHz (–3 dB) is built in 0.8 m CMOS. A 3 V supply is used. The measured midband power gain is 30 dB with 50 resistive source and load impedance. As linearity is important for many modern modulation schemes, the amplifier is designed to be as linear as possible. The measured third order intercept point is 23 dBm and the 1 dB compression point is 10 dBm, both referred to the output. The output is single ended to avoid an off-chip differential to single ended transformer.     

A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules

Much has already been written concerning the IEEE 1149.1Boundary-Scan standard and its application to the detection ofmanufacturing defects [1–3]. However, when circuits such as Multichip Modules (MCMs) which are difficult and expensiveto repair are involved, much more is required of adiagnostic engine than the mere detection of a defect. The cost ofthe dice on a module make it imperative that the diagnostic procedures implemented by a tester be exact. It is not enough tojust state that Node ‹m› isshorted to node ‹n›, or that Node ‹p› is stuck at1, as is frequently the case with printed-circuit boarddiagnostics. MCM diagnostics must examine the data returned fromthe test and, as far as is possible, state not only the symptom ofthe fault, but also its exact cause and location. This articlepresents a set of formalized diagnostic rules which will, wheneverpossible, determine the symptom, cause, and location of amanufacturing defect.     

A copper/polyimide Metal-base packaging technology

A unique substrate MCPM (Mitsubishi Copper Polyimide Metal-base) technology has been developed by applying our basic copper/polyimide technology.¹ This new substrate technology MCPM is suited for a high-density, multi-layer, multi-chip, high-power module/package, such as used for a computer. The new MCPM was processed using a copper metal base (110 × 110 mm), full copper system (all layers) with 50-μm fine lines. As for pad metallizations for the IC assembly, we evaluated both Ni/Au for chip and wire ICs and solder for TAB ICs. The total number of assembled ICs is 25. To improve the thermal dispersion, copper thermal vias are simultaneously formed by electro-plating. This thermal via is located between the IC chip and copper metal base, and promotes heat dispersion. We employed one large thermal via (4.5 mm^?) and four small vias (1.0 mm^?) for each IC pad. The effect of thermal vias and/or base metal is simulated by a computer analysis and compared with an alumina base substrate. The results show that the thermal vias are effective at lowering the temperature difference between the IC and base substrate, and also lowering the temperature rise of the IC chip. We also evaluated the substrate’s reliability by adhesion test, pressure cooker test, etc.     

Fast algorithms for selection of test nodes of an analog circuit using a generalized fault dictionary approach

Selection of test nodes is an important phase of the fault dictionary approach. It is demonstrated in this paper that the techniques used for this purpose in other approaches of analog fault diagnosis like fault analysis and fault verification are not in general suitable for the fault dictionary approach. The ambiguity set is a simple and effective concept for choosing test nodes in the context of dictionaries. These sets are formed such that each faulty condition lies in only one ambiguity set. Deviating from this thinking, overlapping ambiguity sets are proposed in this paper, giving rise to a generalized fault dictionary. These sets use information more fully and hence reduce the number of test nodes. The concept of hashing is applied in this paper for selecting test nodes. This gives a linear time algorithm (linear in the number of fault voltage specificationsf) and it isf times faster than the existing methods. It is not possible to select test nodes faster than this. This technique can also be used to select test nodes by the process of elimination of nodes. This is also linear inf per node elimination. Even a group of nodes can be eliminated or selected within the same computation. This freedom is not possible with the existing methods.     

Pervasive Home Environments

For decades, technologists have been promising the intelligent house. The vision is usually portrayed as a house filled with technology which will do the dweller's bidding and take all domestic drudgery out of their lives. The truly intelligent house is still some way off, but the emergence of broadband, availability of faster, smaller and ever cheaper computing equipment and a variety of wired and wireless network technologies are enabling technologies that bring this vision closer to reality. These technology trends lead to the concept that computing and other smart devices will become pervasive, fully networked and disappear into the infrastructure of the home. People will carry out their tasks unaware of the complexity of the infrastructure that supports their activities in much the same way as people today use mains electricity.This paper introduces these concepts and discusses the technological challenges to be overcome. We present our vision of the pervasive home environment where inhabitants can focus on tasks rather than the technology: I need to create X and send it to Y rather than I need to use this computer and this application which needs access to service A and resource B. Although this sounds simple, the environment needs to understand who I is, and who or what Y is. Appropriate permissions must be in place and resources allocated, if available. The most appropriate interface for the task and user must be determined.The pervasive, intelligent home will make available new ways to access and share information. It will herald new services, such as care and support of people in the home, entertainment, educational and security services. The final part of the paper discusses the commercial opportunities and challenges which must be met, not least the need for industry to agree on open standards and interfaces.     

Lead-free 0201 manufacturing, assembly and reliability test results

The trend towards smaller, faster and cheaper electronic devices has led to an increase in the use of 0201 (L  0.02 in.; W  0.01 in.) and even smaller sized passive components. The size advantages of the 0201 component make it a popular choice among design engineers but not among manufacturing engineers. From a manufacturing perspective, the size of the 0201 package poses significant challenges to the printed circuit board (PCB) assembly process. The many challenges with 0201 assembly can be attributed to the solder paste volume, pad design, aperture design, board finish, type of solder paste, pick-and-place and reflow profile. If these factors are not optimized, they will introduce undesirable manufacturing defects. The small size of 0201 packages and undetected manufacturing defects will also raise concerns about their second level interconnect reliability, especially for lead-free solder alloys and surface finishes, with new processes and higher reflow requirements. To determine the optimum conditions, a design-of-experiment (DOE) study was carried out to investigate the effects of these parameters on assembly defects and solder joint reliability.This paper presents the test results and comparative literature data on the influence of a few key manufacturing parameters and defects associated with the 0201 component using lead-free and tin–lead solder alloys. Data pertaining to component shear strength before and after isothermal aging at 150 °C and intermetallic growth up to 500 h of aging are presented. A number of test vehicles were also subjected to thermal cycling (1500 cycles) in the range of −55/100 °C to determine the solder fatigue behavior. Shear test results for test vehicles subjected to thermal cycling is also presented. In addition, optical microscopy analysis of solder joint behavior during thermal cycling showing the progress of the solder damage and cross-sectional photos taken at 1500 cycles is included.     

The Supply Chain

One of the most visible examples of ubiquitous computing poised for implementation can be found in the retail industry. Radio frequency identification (RFID) tags are being billed as the replacement for barcoding, the all-pervasive technology which has underpinned supply chains for the past 35 years. The standards allow for up to thirty trillion, trillion, trillion unique addresses, and the ultimate goal is to create an Internet of things in which everyday physical items are networked together. Concerted research effort over the past five years has developed the technology and reduced cost to a point where deployment is now possible. However, the recent heated debate centred on spy chips has highlighted the fact that one person's ubiquitous computing is another person's Big Brother state.     

SRAM-Based FPGAs: Testing the Embedded RAM Modules

This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Targeting the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the March tests. We also propose a unique test configuration called pseudo shift register for an m × m array of modules. In the proposed configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called shifted MATS++ is described.     

晶圆上测试射频系统级芯片的挑战(英文)

随着无线通讯产业推动芯片集成度的不断提高,系统级封装(SIP)和多芯片组件(MCM)被更多采用,射频系统级芯片(RF-SOC)器件的良品测试已成为一大挑战。这些器件与传统的单晶片集成电路相比,具有更高的封装成本,并且由于采用多个晶片,成品率较低。其结果是进行晶圆上综合测试的成本远超过最终封装后测试器件的成本。此外,一些IC制造商销售裸晶片以用于另一些制造商的SIP和MCM中,这就要求发货的产品必须是良品。以蓝牙射频调制解调芯片为例,讨论了RF-SOC器件良品晶片(KGD)的测试难点和注意事项。对此样品,除了在晶圆上进行射频功能测试的难点,还有同时发射和测量数字、射频信号的综合问题。此外对被测器件(DUT)用印制线路板布线的难点,包括晶圆探针卡的设置及装配进行探讨。还介绍了选择探针测试台、射频晶圆探针卡和自动测试设备(ATE)时需考虑的因素。并以晶圆上测试的系统校正,包括难点和测试方法,作为结尾。这颗蓝牙射频调制解调芯片的实际测试数据也会被引用,以佐证和加深文章中的讨论。     

Economic modeling of board test strategies

A long and deep recession, coupled with continuous competitive pressure to reduce costs, is forcing many companies to review their test strategies. Testing costs have become a more significant proportion of the overall manufacturing cost even though manufacturing yields have increased dramatically over the past ten or twelve years. This causes attention to be focused on testing costs as a key source of cost reduction. The increased use of DFT and the integration of design and test are very positive moves towards controlling testing costs but other methods employed can often backfire. The increased use of low priced testers is one such method. The pressure to reduce costs, higher process yields and exhortations that testing adds no value can lead the test engineering manager to take the cheap route. In reality this can often turn out to be an expensive decision. The only way to avoid expensive mistakes is to perform an economic analysis of the alternative courses of action. In most cases this is done, but not always in the right manner or with the necessary amount of detail to make the comparisons meaningful. This article discusses the need for effective cost analysis of test strategies and highlights some of the pitfalls.