Back‐channel‐etched thin‐film transistor using c‐axis‐aligned crystal In–Ga–Zn oxide

Our crystalline In–Ga–Zn oxide (IGZO) thin film has a c‐axis‐aligned crystal (CAAC) structure and maintains crystallinity even on an amorphous base layer. Although the crystal has c‐axis alignment, its a‐axis and b‐axis have random arrangement; moreover, a clear grain boundary is not observed. We fabricated a back‐channel‐etched thin‐film transistor (TFT) using the CAAC‐IGZO film. Using the CAAC‐IGZO film, more stable TFT characteristics, even with a short channel length, can be obtained, and the instability of the back channel, which is one of the biggest problems of IGZO TFTs, is solved. As a result, we improved the process of manufacturing back‐channel‐etched TFTs.     

Circuits using uniform TFTs based on amorphous In‐Ga‐Zn‐O

Abstract— High‐performance and excellent‐uniformity thin‐film transistors (TFTs) having bottom‐gate structures are fabricated using an amorphous indium‐gallium‐zinc‐oxide (IGZO) film and an amorphous‐silicon dioxide film as the channel layer and the gate insulator layer, respectively. All of the 94 TFTs fabricated with an area 1 cm² show almost identical transfer characteristics: the average saturation mobility is 14.6 cm²/(V‐sec) with a small standard deviation of 0.11 cm²/(V‐sec). A five‐stage ring‐oscillator composed of these TFTs operates at 410 kHz at an input voltage of 18 V. Pixel‐driving circuits based on these TFTs are also fabricated with organic light‐emitting diodes (OLED) which are monolithically integrated on the same substrate. It is demonstrated that light emission from the OLED cells can be switched and modulated by a 120‐Hz ac signal input. Amorphous‐IGZO‐based TFTs are prominent candidates for building blocks of large‐area OLED‐display electronics.     

Solution‐processed oxide semiconductors for low‐cost and high‐performance thin‐film transistors and fabrication of organic light‐emitting‐diode displays

Abstract— High‐performance solution‐processed oxide‐semiconductor (OS) thin‐film transistors (TFTs) and their application to a TFT backplane for active‐matrix organic light‐emitting‐diode (AMOLED) displays are reported. For this work, bottom‐gated TFTs having spin‐coated amorphous In‐Zn‐O (IZO) active layers formed at 450°C have been fabricated. A mobility (μ) as high as 5.0 cm²/V‐sec, ?0.5 V of threshold voltage (VT), 0.7 V/dec of subthreshold swing (SS), and 6.9 × 10⁸ of on‐off current ratio were obtained by using an etch‐stopper (ES) structure TFT. TFTs exhibited uniform characteristics within 150 × 150‐mm² substrates. Based on these results, a 2.2‐in. AMOLED display driven by spin‐coated IZO TFTs have also been fabricated. In order to investigate operation instability, a negative‐bias‐temperature‐stress (NBTS) test was carried out at 60°C in ambient air. The IZO‐TFT showed ?2.5 V of threshold‐voltage shift (ΔVT) after 10,800 sec of stress time, comparable with the level (ΔVT = ?1.96 V) of conventional vacuum‐deposited a‐Si TFTs. Also, other issues regarding solution‐processed OS technology, including the instability, lowering process temperature, and printable devices are discussed.     

Single‐source dual‐layer amorphous IGZO thin‐film transistors for display and circuit applications

In this study, the authors report on high‐quality amorphous indium–gallium–zinc oxide thin‐film transistors (TFTs) based on a single‐source dual‐layer concept processed at temperatures down to 150°C. The dual‐layer concept allows the precise control of local charge carrier densities by varying the O₂/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual‐layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual‐layer TFTs are more stable under bias conditions in comparison with single‐layer TFTs processed at low temperatures. Finally, the applicability of this dual‐layer concept in logic circuitry such as 19‐stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active‐matrix organic light‐emitting diode display demonstrator is proven.     

Active‐matrix organic light‐emitting diode displays with indium gallium zinc oxide thin‐film transistors and normal,inverted, and transparent organic light‐emitting diodes

Abstract— Active‐matrix organic light‐emitting diode (AMOLED) displays have gained wide attention and are expected to dominate the flat‐panel‐display industry in the near future. However, organic light‐emitting devices have stringent demands on the driving transistors due to their current‐driving characteristics. In recent years, the oxide‐semiconductor‐based thin‐film transistors (oxide TFTs) have also been widely investigated due to their various benefits. In this paper, the development and performance of oxide TFTs will be discussed. Specifically, effects of back‐channel interface conditions on these devices will be investigated. The performance and bias stress stability of the oxide TFTs were improved by inserting a SiO^x protection layer and an N²O plasma treatment on the back‐channel interface. On the other hand, considering the n‐type nature of oxide TFTs, 2.4‐in. AMOLED displays with oxide TFTs and both normal and inverted OLEDs were developed and their reliability was studied. Results of the checkerboard stimuli tests show that the inverted OLEDs indeed have some advantages due to their suitable driving schemes. In addition, a novel 2.4‐in. transparent AMOLED display with a high transparency of 45% and high resolution of 166 ppi was also demonstrated using all the transparent or semi‐transparent materials, based on oxide‐TFT technologies.     

Flexible AMOLEDs with low‐temperature‐processed TFT backplane technologies

Developments of backplane technologies, which are one of the challenging topics, toward the realization of flexible active matrix organic light‐emitting diodes (AMOLEDs) are discussed in this paper. Plastic substrates including polyimide are considered as a good candidate for substrates of flexible AMOLEDs. The fabrication process flows based on plastic substrates are explained. Limited by the temperature that plastic substrates can sustain, TFT technologies with maximum processing temperature below 400 °C must be developed. Considering the stringent requirements of AMOLEDs, both oxide thin‐film transistors (TFTs) and ultra‐low‐temperature poly‐silicon TFTs (U‐LTPS TFTs) are investigated. First, oxide TFTs with representative indium gallium zinc oxide channel layer are fabricated on polyimide substrates. The threshold voltage shifts under bias stress and under bending test are small. Thus, a 4.0‐in. flexible AMOLED is demonstrated with indium gallium zinc oxide TFTs, showing good panel performance and flexibility. Further, the oxide TFTs based on indium tin zinc oxide channel layer with high mobility and good stability are discussed. The mobility can be higher than 20 cm²/Vs, and threshold voltage shifts under both voltage stress and current stress are almost negligible, proving the potential of oxide TFT technology. On the other hand, the U‐LTPS TFTs are also developed. It is confirmed that dehydrogenation and dopant activation can be effectively performed at a temperature within 400 °C. The performance of U‐LTPS TFTs on polyimide is compatible to those of TFTs on glass. Also, the performance of devices on polyimide can be kept intact after devices de‐bonded from glass carrier. Finally, a 4.3‐in. flexible AMOLED is also demonstrated with U‐LTPS TFTs.     

Active‐matrix organic light‐emitting diode using inverse‐staggered poly‐Si TFTs with a center‐offset gated structure

Abstract— A low‐cost active‐matrix backplane using non‐laser polycrystalline silicon (poly‐Si) having inverse‐staggered TFTs with amorphous‐silicon (a‐Si) n⁺ contacts has been developed. The thin‐film transistors (TFTs) have a center‐offset gated structure to reduce the leakage current without scarifying the ON‐currents. The leakage current of the center‐offset TFTs at Vg = ?10 V is two orders of magnitude lower than those of the non‐offset TFTs. The center‐offset length of the TFTs was 3 μm for both the switching and driving TFTs. A 2.2‐in. QQVGA (1 60 × 1 20) active‐matrix organic light‐emitting‐diode (AMOLED) display was demonstrated using conventional 2T + 1C pixel circuits.     

12.1‐in. WXGA AMOLED display driven by InGaZnO thin‐film transistors

Abstract— A full‐color 12.1‐in.WXGA active‐matrix organic‐light‐emitting‐diode (AMOLED) display was, for the first time, demonstrated using indium‐gallium‐zinc oxide (IGZO) thin‐film transistors (TFTs) as an active‐matrix backplane. It was found that the fabricated AMOLED display did not suffer from the well‐known pixel non‐uniformity in luminance, even though the simple structure consisting of two transistors and one capacitor was adopted as the unit pixel circuit, which was attributed to the amorphous nature of IGZO semiconductors. The n‐channel a‐IGZO TFTs exhibited a field‐effect mobility of 17 cm²/V‐sec, threshold voltage of 1.1 V, on/off ratio >10⁹, and subthreshold gate swing of 0.28 V/dec. The AMOLED display with a‐IGZO TFT array is promising for large‐sized applications such as notebook PCs and HDTVs because the a‐IGZO semiconductor can be deposited on large glass substrates (larger than Gen 7) using the conventional sputtering system.     

Comparative study of source–drain contact metals for amorphous InGaZnO thin‐film transistors

In this work, we compared the thin‐film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source–drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom‐gate bottom‐contact (BGBC) and bottom‐gate top‐contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a‐IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal‐containing deposits in the channel and the contact oxidation during a‐IGZO layer sputtering in the presence of S/D metal. In bias‐stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal‐containing deposits at the backchannel during the final the SiO₂ passivation.     

Novel back‐channel‐etch process flow based a‐IGZO TFTs for circuit and display applications on PEN foil

In this study, we report high‐quality amorphous indium–gallium–zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) fabricated on a polyethylene naphthalate foil using a new back‐channel‐etch (BCE) process flow. The BCE flow allows a better scalability of TFTs for high‐resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165 °C in order to ensure good overlay accuracy (<1 µm) on foil. The presented process flow differs from the previously reported flow as we define the Mo source and drain contacts by dry etch prior to a‐IGZO patterning. The TFTs show good electrical performance, including field‐effect mobilities in the range of 15.0 cm²/(V·s), subthreshold slopes of 0.3 V/decade, and off‐currents <1.0 pA on foil. The threshold voltage shifts of the TFTs measured were less than 1.0 V after a stressing time of 10⁴ s in both positive (+1.0 MV/cm) and negative (?1.0 MV/cm) bias directions. The applicability of this new BCE process flow is demonstrated in a 19‐stage ring oscillator, demonstrated to operate at a supply voltage of 10 V with a stage delay time of 1.35 µs, and in a TFT backplane driving a 32 × 32 active‐matrix organic light‐emitting diode display.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

Modeling of threshold‐voltage‐shift dependency on drain bias in amorphous‐silicon thin‐film transistors in active‐matrix organic light‐emitting‐diode displays

Abstract— A theoretical model to interpret appearances of the threshold voltage shift in hydrogenated amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) is developed to better understand the instability of a‐Si:H TFTs for the driving transistors in active‐matrix organic light‐emitting‐diode (AMOLED) displays. This model assumes that the defect creation at channel in a‐Si:H is proportional to the carrier concentration, leading to the defect density varying along the channel depending on the bias conditions. The model interprets a threshold‐voltage‐shift dependency on the drain‐stress bias. The model predicts the threshold voltage shift stressed under a given gate bias applying the drain saturation voltage is 66% of that with zero drain bias, and it even goes down to 50–60% of that when stressed by applying twice the drain saturation voltage.     

Relationship between crystallinity and device characteristics of In‐Sn‐Zn oxide

We have reported that the transistors having the c‐axis‐aligned crystalline (CAAC) In‐Ga‐Zn oxide (IGZO) show good performance. Recently, In‐Sn‐Zn Oxide (ITZO) has attracted much attention because of its high electron mobility, as well as IGZO. However, it has been reported that ITZO field effect transistors (FET) tend to have positive Vth (normally‐on characteristics) and poor reliability compared with IGZO‐FETs. We have reported that high‐performance and high‐reliability OS‐FETs can be fabricated by using CAAC‐IGZO, which has high crystallinity and has no clear grain boundaries, as an active layer. Therefore, we have fabricated CAAC‐ITZO thin films to improve performance of ITZO‐FETs by using CAAC‐ITZO as an active layer. In addition, FETs employing CAAC‐ITZO have better characteristics and reliability than FETs using nano‐crystal ITZO. Furthermore, constant photocurrent method (CPM) measurement was carried out in order to estimate density of deep‐level defect states caused by oxygen vacancies in oxide semiconductors. The results show that CAAC‐ITZO has lower density of deep‐level defect states than nano‐crystal ITZO. We attribute the improvement in reliability of ITZO‐FETs to a decrease in deep‐level defect states of an ITZO active layer, as is the case with IGZO.     

Effect on electrical performance of titanium co‐sputtered IZO active‐channel thin‐film transistor

We investigated the electrical performance of Ti–IZO active‐channel layer thin‐film transistors (TFTs) using a radio frequency (RF) magnetron co‐sputtering system to co‐sputter IZO and Ti targets. The samples were fabricated by changing the RF gun power of the IZO. The other parameters such as the RF gun power of the Ti target, oxygen partial pressure [O₂/(Ar + O₂)], and initial and process pressure of the chamber were unchanged. Unlike the sample sputtered only with IZO, the thin films of the Ti–IZO samples could control the oxygen vacancy because Ti reacts with the oxygen in the IZO. Therefore, Ti–IZO thin films can suppress the carrier concentration and thus have an effect on the electrical performance of TFTs.     

High‐mobility self‐aligned top‐gate oxide TFT for high‐resolution AM‐OLED

High‐mobility and highly reliable self‐aligned top‐gate oxide thin‐film transistor (TFTs) were developed using the aluminum reaction method. Al diffusion to the oxide semiconductor and homogenization of the oxygen concentration in the depth direction after annealing were confirmed by laser‐assisted atom probe tomography. The high mobility of the top‐gate TFT with amorphous indium tin zinc oxide channel was demonstrated to be 32 cm²/V s. A 9.9‐in. diagonal qHD active‐matrix organic light‐emitting diode (AM‐OLED) display was fabricated using a five‐mask backplane process to demonstrate an applicable solution for large‐sized and high‐resolution AM‐OLEDs.     

Suspension‐deposited carbon‐nanotube networks for flexible active‐matrix displays

Abstract— The unique properties of carbon nanotubes (CNTs) promise innovative solutions for a variety of display applications. The CNTs can be deposited from suspension. These simple and low‐cost techniques will replace time‐consuming and costly vacuum processes and can be applied to large‐area glass and flexible substrates. Single‐walled carbon nanotubes (SWNTs) have been used as conducting and transparent layers, replacing the brittle ITO, and as the semiconducting layer in thin‐film transistors (TFTs). There is no need for alignment because a CNT network is used instead of single CNTs. Both processes can be applied to glass and to flexible plastic substrates. The transparent and conductive nanotube layers can be produced with a sheet resistance of 400 Ω/□ at 80% transmittance. Such layers have been used to produce directly addressed liquid‐crystal displays and organic light‐emitting diodes (OLED). The CNT‐TFTs reach on/off ratios of more than 10⁵ and effective charge‐carrier mobilities of 1 cm²/V‐sec and above.     

Novel self‐aligned top‐gate oxide TFT for AMOLED displays

Abstract— A novel highly reliable self‐aligned top‐gate oxide‐semiconductor thin‐film transistor (TFT) formed by using the aluminum (Al) reaction method has been developed. This TFT structure has advantages such as small‐sized TFTs, lower mask count, and small parasitic capacitance. The TFT with a 4‐μm channel length exhibited a field‐effect mobility of 21.6 cm²/V‐sec, a threshold voltage of ?1.2 V, and a subthreshold swing of 0.12 V/decade. Highly reliable TFTs were obtained after 300°C annealing without increasing the sheet resistivity of the source/drain region. A 9.9‐in.‐diagonal qHD AMOLED display was demonstrated with self‐aligned top‐gate oxide‐semiconductor TFTs for a low‐cost and ultra‐high‐definition OLED display. Excellent brightness uniformity could be achieved due to small parasitic capacitance.     

Amorphous‐oxide TFT backplane for large‐sized AMOLED TVs

Abstract— Amorphous‐oxide thin‐film‐transistor (TFT) arrays have been developed as TFT backplanes for large‐sized active‐matrix organic light‐emitting‐diode (AMOLED) displays. An amorphous‐IGZO (indium gallium zinc oxide) bottom‐gate TFT with an etch‐stop layer (ESL) delivered excel lent electrical performance with a field‐effect mobility of 21 cm²/V‐sec, an on/off ratio of >10⁸, and a subthreshold slope (SS) of 0.29 V/dec. Also, a new pixel circuit for AMOLED displays based on amorphous‐oxide semiconductor TFTs is proposed. The circuit consists of four switching TFTs and one driving TFT. The circuit simulation results showed that the new pixel circuit has better performance than conventional threshold‐voltage (VTH) compensation pixel circuits, especially in the negative state. A full‐color 19‐in. AMOLED display with the new pixel circuit was fabricated, and the pixel circuit operation was verified in a 19‐in. AMOLED display. The AMOLED display with a‐IGZO TFT array is promising for large‐sized TV because a‐IGZO TFTs can provide a large‐sized backplane with excellent uniformity and device reliability.     

Characteristics improvement of top‐gate self‐aligned amorphous indium gallium zinc oxide thin‐film transistors using a dual‐gate control

In this work, we have reported dual‐gate amorphous indium gallium zinc oxide thin‐film transistors (a‐IGZO TFTs), where a top‐gate self‐aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a‐IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (I_ON), sub‐threshold slope (SS^?1), output resistance, and bias‐stress instabilities are improved in comparison with single‐gate control self‐aligned a‐IGZO TFTs. We have also investigated the applicability of the dual‐gate a‐IGZO TFTs in logic circuitry such as 19‐stage ring oscillators.     

Effects of post‐annealing on a‐Si:H TFT characteristics fabricated on stainless‐steel substrate

Abstract— A 14.1‐in.‐diagonal backplane employing hydrogenated amorphous‐silicon thin‐film transistors (a‐Si:H TFTs) was fabricated on a flexible stainless‐steel substrate. The TFTs exhibited a field‐effect mobility of 0.54 cm²/V‐sec, a threshold voltage of 1.0 V, and an off‐current of 10^?13 A. Most of the electrical characteristics were comparable to those of the TFTs fabricated on glass substrates. To increase the stability of a‐Si:H TFTs fabricated on stainless‐steel substrate, the specimens were thermally annealed at 230°C. The field‐effect mobility was reduced to 71% of the initial value because of the strain of the released hydrogen atoms and residual compressive stress in a‐Si:H TFT under thermal annealing at 230°C.