容许两个盘故障的磁盘阵列数据布局与图分解的条件和存在性研究

从一个新的途径讨论容许两个盘故障的磁盘阵列数据布局：把由数据单元和通过“异或”运算得到的校验单元组成的校验组用一个图表示，把校验组容许两个盘故障的阵列布局归结为校验组的单元集合的划分，进而转化为校验组的图的顶点和边组成集合的满足一定条件的分解．证明了校验组容许两个盘故障的单元集合划分的充分必要条件及存在性；讨论了优化阵列布局方案性能的条件；给出了阵列布局的步骤．从而为设计具有最优性能的容许两个盘故障的磁盘阵列数据布局方案提供了有效的途径．     

输入端加译码器的可编程逻辑阵列的复杂性分析

输入端加译码器的可编程逻辑阵列比普通的可编程逻辑阵列具有更大的实现能力。这种阵列表现为三级或－与－或电路。本文提出了与该电路相关的一系列基本概念和理论，并且还进行了复杂性分析，结论是使用该阵列实现一个任意Ｎ变量逻辑函数所需的最大存储单元数为：（２ｎ＋１）２＾ｎ－２．     

连续电驱动四足机器人腿部机构设计与分析

提出了一种四足机器人腿部的连续电驱动（即电机整周转动驱动腿部实现摆转跨步动作）方案,设计了一种具有由切比雪夫机构、五杆机构组成的2自由度双曲柄复合连杆机构的机器人腿部结构．分析了动物的足端轨迹特性,采用轨迹圆滑、无突变、导数连续的椭圆曲线规划了机器人足端运动轨迹．以规划的足端轨迹再现为优化目标,采用遗传算法与fmincon函数内点法计算得到了腿部机构杆长的最佳尺寸．在此基础上,建立了机器人仿真模型,通过Adams仿真分析了机器人腿部机构的足端运动特性,并研制了腿部结构性能测试平台．完成了单腿足端运动轨迹跟踪实验,验证了腿部结构设计方案的可行性．     

基于SNMP的VLC视频流转码设计和实现

讨论了在Internet上进行网络设备管理的问题，描述了在Linux 9．0环境下，基于UCD-SNMP，使用VLC软件，根据远程用户的需求和VLC转码板提供的功能，实现对VLC转码板的代理端MIB库扩展，以及网络管理端的设计。测试实验证明了所提方案的有效性。     

万兆以太网物理层编码芯片设计

提出了一种并行处理的编解码方案。采用这种方案．设计了万兆以太网10GBASE-R标准的物理编码子层发送端芯片。芯片由64b／66b编码、扰码和变速箱3部分组成。考虑到测试问题，该芯片内置了伪随机码数据源。这种方案的优点是逻辑简单、速度快。芯片采用TSMC 0.18μmCMOS工艺，用全定制方式实现。芯片引脚分布时参照PLCC48规格。     

CSA/CLA阵列乘法器的测试生成

文中针对最后一级采用４位ＣＬＡ加法器级联的Ｍ×Ｎ位ＣＳＡ／ＣＬＡ阵列乘法器,讨论了一种非常有效的测试生成方法．该方法不依赖于乘法器的大小以及乘法器基本单元内部的具体实现结构,与前人的工作相比,缩短了测试时间．对于上述结构的ＣＳＡ／ＣＬＡ阵列乘法器,使用２８个测试矢量即可得到１００％的故障覆盖率．采用文中给出的测试矢量构造ＣＳＡ／ＣＬＡ阵列乘法器的ＢＩＳＴ电路不需要改变乘法器的结构,因此对乘法器的正常工作性能几乎没有任何影响．     

射频平面阵列目标位置控制系统的研究

阵列式射频仿真技术开始用于论证大型设备在复杂电磁环境下的效能评估试验,常规单一试验中心的球面阵列已难以适应此类试验,迫切需要构造一种新型阵列系统来完成新的试验,为此提出采用射频平面阵列式目标位置控制方案.设计并制作了平面阵列结构,论述了目标位置控制系统的阵列馈电方案以及软件模块,重点阐述了精位控制算法和粗位控制原理.提出四元组合成方案实现精位控制,并推导了四元组合成位置的角闪烁方程.最后在微波暗室内测试了典型频段下该系统的辐射信号合成角位置精度,结果表明该阵列系统在X波段的角位置模拟精度可达1 mrad,能够用于大型设备的效能评估试验.     

使用TTCN-3的端到端性能测试系统

介绍了网络端到端性能测试的基本概念和方法。在一致性测试框架上，使用TTCN-3测试语言，设计了端到端性能测试系统TTPerf。它的测试结构灵活，测试套开发方便。     

微热板阵列式集成气体传感器的芯片电路设计

针对加热测温一体化集成微热板阵列气体传感器的需要,以微热板加热性能测试参数为依据,提出了一种基于微热板气体传感器阵列的单片集成方案。该方案包括由四个微热板构成的传感器阵列,加热驱动单元和信号采集单元。采用Hspice软件对加热驱动电路和信号采集电路进行设计,并进行了芯片电路系统的仿真。仿真结果表明实现了微热板的独立控温和信号的采集,验证了该方案的可行性和正确性。     

比较线性相位完全重构滤波器阵列在图象编码中的应用

比较了两种不同类型的多通道线性相位完全重构滤波器阵列在图象编码中的应用。由于图象的绝大部分能量集中低于频端,我们发现低频端滤波器的长度大于高频端滤波器长度的线性相位完全重构滤波器阵列比各个通道滤波器长度相同的滤波器阵列有较 编码效果。     

Fast and energy-frugal deterministic test through efficient compression and compaction techniques

Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthermore, the transitions that occur in the scan chains during these shifts reflect into significant levels of circuit switching unnecessarily, increasing the power dissipated. Judicious encoding of the correlation among the test vectors and construction of a test vector through predecessor updates helps reduce not only test application time but also scan chain transitions as well. Such an encoding scheme, which additionally reduces test data volume, can be further enhanced through appropriately ordering and padding of the test cubes given. The experimental results confirm the significant reductions in test application time, test data volume and test power achieved by the proposed compression methodology.     

CrossCheck: an innovative testability solution

CrossCheck, an approach to the application-specific integrated circuit ASIC test problem that is based on embedding test structures into the base array of the ASIC, is discussed. With a specially designed storage element called the cross-controlled latch, CrossCheck combines controllability and observability to produce a highly testable ASIC having minimal area and performance overhead. CrossCheck is a designer-transparent solution that imposes none of the rules and restrictions of other design-for-testability (DFT) methodologies. In CrossCheck, test structures are embedded into the ASIC base, rather than added by the designer to the schematic as with scan or built-in self-test (BIST) methodologies. The built-in observability also offers easier debugging and diagnostics methods to the designer. Experimental results that demonstrate the potential of the CrossCheck method on a broad range of ASIC styles and sizes are presented     

Simple analog-digital motion detection circuit and its application to target tracking systems

We propose an analog-digital circuit for detecting the movement of an object. The proposed unit circuit is a simple structure since the digital part of the circuit is constructed with only one NOT circuit and one NOR circuit. The measured results on a constructed test circuit showed that the proposed circuit can output the pulsed voltage (motion signal) when an object moves on the circuit. We proposed and constructed the system in this study in order to track target. Since the array in the proposed circuits was introduced at the first stage of the system, the circuit for tracking the target became a simple structure. It was clear from the measured results of the test system that it can track and capture a target in the center of the input section.     

多传感轨道扣件检测的数据同步采集系统设计

针对轨道扣件检测的多传感数据同步采集,首先,在分析线阵CCD相机成像原理的基础上,根据系统的要求对相机的关键参数进行了选择并设计了采集方案。然后,设计了传感器的信号调理电路,包括电平调整电路以及抗混叠滤波器的设计,提高了传感器的抗干扰能力。并通过STM32获取光电编码器的等间隔脉冲信息,对各个传感器进行触发控制,设计了线阵相机与惯性传感器的同步触发方案。最后,编写了上位机软件实现了数据的同步采集。实验结果表明,该系统能够精确采集各传感器的数据,具有较强的抗干扰能力和稳定性。     

基于响应分块相容的测试数据编码压缩方案

提出一种测试数据压缩方案,利用测试向量与扫描链中响应数据的分块相容来增加被编码测试向量中的无关位,降低了线性反馈移位寄存器（LFSR）编码种子的度数,且不必增加额外的测试向量,最终达到压缩测试数据的目的．该方案的硬件解压结构仅需一个LFSR和简单的控制电路．实验结果表明,与其他压缩方法,如基于部分向量切分的LFSR重新播种方法、混合码方案和FDR码方案等相比,该方案在压缩效率和硬件开销上都有明显优势．     

Modular array structure for non-restoring square root circuit

Square root is an operation performed by the hardware in recent generations of processors. The hardware implementation of the square root operation is achieved by different means. One of the popular methods is the non-restoring algorithm. In this paper, the classical non-restoring array structure is improved in order to simplify the circuit. This reduction is done by eliminating a number of circuit elements without any loss in the precision of the square root or the remainder. For a 64-bit non-restoring circuit the area of the suggested circuit is about 44% smaller than that of a conventional non-restoring array circuit. Furthermore, in order to create an environment for modular design of the non-restoring square root circuit, a number of modules are suggested. Using these modules it is possible to construct any square root circuit with an arbitrary number of input bits. The suggested methodology results in an expandable design with reduced-area. Analytical and simulation results show that the delay of the proposed circuit, for a 64-bit radicand, is 80% less than that of a conventional non-restoring array circuit.     

Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process基于65纳米CMOS工艺的静态触发型电源钳位ESD保护电路设计

This work presents the design of a novel static-triggered power-rail electrostatic discharge (ESD) clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit (TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current (I_leak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.     

基于部分测试向量切分的LFSR重新播种方法

提出一种测试码压缩方法,首先切分测试集中含确定位较多的难以编码的测试向量,然后与未被切分的测试向量共同组成新的测试集,并将新测试集编码成线性反馈移位寄存器(LFSR)种子,从而实现测试数据压缩.该方法提高了LFSR的编码效率,取得了稍优于混合码的压缩率.与混合码复杂的解压结构相比,在硬件开销上具有明显的优势,仅需一个LFSR和简单的控制电路,且通信协议简单.     

Beamforming of UWB pulse array and its implementation

This paper firstly introduces a realistic ultra-wideband (UWB) pulse model and discusses the principle of sensor array beamforming for UWB pulse signals. Then the differences between a UWB pulse array and narrowband sinusoidal array are studied. Based on it, the problem of realizing a digital and applicable variable delay circuit (VDC) to compensate the channel propagation delay accurately for UWB pulse array beamforming is addressed. In our work, fractional sample delay compensation filters (FDCF) are combined with delay lines to build up accurate VDCs. As a result, the Lagrange interpolation method based on maximally flat criterion is found to be most suitable for the fixed beam steering; and Farrow structure is recommended to satisfy the need of rapid beam adjustment. In the simulation experiments, two kinds of directivity pattern for an UWB pulse array are studied and compared with that of sinusoidal array. The effectiveness of the presented scheme is verified by the simulation results, which show that the VDC implementation by digital lines and FDCF can remarkably improve the performance of the directivity patterns of UWB pulse array especially for the system with low sampling rate.