电荷俘获存储器阻挡层研究进展

随着非挥发性存储器(NVM)存储单元的特征尺寸进入20 nm节点,使用单层SiO2作为阻挡层的传统电荷俘获存储器结构性能上逐渐受到限制。基于阻挡层在存储器栅堆栈中的作用与基本要求,首先,指出单层SiO2作为阻挡层存在的主要问题,然后对高介电常数材料作为阻挡层时,其禁带宽度、介电常数、内部的缺陷密度以及退火工艺等方面对存储特性的影响进行了分析,同时对近年来研究较多的阻挡层能带工程进行了详细介绍,如SiO2和Al2O3的复合阻挡层结构、多层高介电常数材料的阻挡层结构等。最后,对目前研究进展中存在的问题以及未来的研究方向和趋势进行了总结和展望。     

高k介质在浮栅型非挥发性存储器中的应用

随着微电子技术节点不断向前推进,基于传统浮栅结构的非挥发性存储器(NVM)技术遇到严重的技术难点,其中最主要的问题是SiO2隧穿层已经接近厚度极限,很难继续减薄.作为改进措施,引入高k介质作为新型隧穿层材料.文章介绍了高k材料的研究现状和在NVM器件中应用所取得的进展;最后,对高k介质进一步应用的研究趋势进行了展望.     

Al/SRO/Si结构中横向电压作用下的电荷俘获效应

利用Al/ SRO/ Si MOS,对富硅二氧化硅(SRO)材料在横向电压作用下的电荷俘获效应进行了研究.用L PCVD法在n型Si衬底上沉积SRO材料,通过C- V测量研究其电荷俘获性质.发现对于n型Si衬底,在横向电压作用下,SRO层能够俘获正电荷,电荷俘获效应与SRO层的性质有关.基于电位在器件内部的分布及诱导pn结的形成,提出了一个简单的物理模型来解释所得到的实验结果     

Al/SRO/Si结构中横向电压作用下的电荷俘获效应

利用Al/SRO/Si MOS,对富硅二氧化硅(SRO)材料在横向电压作用下的电荷俘获效应进行了研究.用LPCVD法在n型Si衬底上沉积SRO材料,通过C-V测量研究其电荷俘获性质.发现对于n型Si衬底,在横向电压作用下,SRO层能够俘获正电荷,电荷俘获效应与SRO层的性质有关.基于电位在器件内部的分布及诱导pn结的形成,提出了一个简单的物理模型来解释所得到的实验结果.     

高k棚介质中电荷俘获行为的脉冲特征分析

本文介绍了电荷俘获的原理以及直流特征分析技术对俘获电荷进行定量分析的局限性,同时介绍了脉冲I-V分析技术,其能够对具有快速瞬态充电效应(FTCE)的高k栅晶体管的本征(无俘获)性能进行特征分析.     

CTM俘获层材料选取的模拟研究

电荷陷阱存储器(CTM)由于其分离式电荷存储原理,可以使存储器件尺寸持续小尺寸化,理论上解决了传统浮栅存储器小尺寸化瓶颈的限制。基于第一性原理,从理论上对CTM材料及相关结构进行了模拟计算,采用Material Studio软件包,对多种电荷俘获材料进行改性,引入陷阱,并对其能带、状态密度、缺陷态密度等方面展开模拟研究。为CTM实验提供了非常有效的理论依据与方法,从该角度出发研究存储器是一个全新的视角,提出可以通过陷阱态密度曲线的部分积分来确定CTM的存储窗口等衡量指标。     

FLOTOXEEPROM擦写过程中隧道氧化层陷阱俘获电荷的研究

本文首先从理论上分析FLOTOX EEPROM隧道氧化层中陷阱俘获电荷对注入电场和存储管阈值电压的影响,然后给出了在不同擦写条件下FLOTOX EEPROM存储管的阈值电压与擦写周期关系的实验结果,接着分析了在反复擦写过程中陷阱俘获电荷的产生现象.对于低的擦写电压,擦除阈值减少,在隧道氧化层中产生了负的陷阱俘获电荷;对于高的擦写电压,擦除阈值增加,产生了正陷阱俘获电荷.这一结果与SiO₂中电荷的俘获——解俘获动态模型相吻合.     

77KFowler—Nordheim电子注入和栅氧化层俘获特性研究

本研究了７７Ｋ下薄栅ＮＭＯＳＦＥＴ在Ｆ－Ｎ均匀注入时栅氧化层对电荷的俘获特性，发现沟道区上方栅氧化屋将俘获电荷，使阀值电压下降，而栅边缘氧化层地电子的俘获明显增强，并高于室温一的对应值，从而导致ＮＭＯＳＦＥＴ关态特性变差，沟道电阻增大，以及电流驱动能力的显降低，提出了栅边缘氧化层增强电子俘获的深能级中性陷机制。     

利用改进的电荷泵法研究SONOS存储器陷阱电荷的分布特性

在silicon-oxide-nitride-oxide-silicon(SONOS)等电荷俘获型不挥发存储器中,编程操作后注入电荷的分布会对器件的读取、擦写以及可靠性带来影响.利用电荷泵方法可以有效而准确地测量出注入电荷沿沟道方向的分布.为了提高测试精度,在进行电荷泵测试时,采用固定低电平与固定高电平相结合的方法,分别对SONOS器件源端和漏端进行注入电荷分布的测试.通过测试,最终获得SONOS存储器在沟道热电子注入编程后的电子分布.电子分布的峰值区域在漏端附近,分布宽度在50nm左右.     

金属纳米晶快闪存储器研究进展

金属纳米晶具有态密度高、费米能级选择范围广以及无多维载流子限制效应等优越性,预示着金属纳米晶快闪存储器在下一代闪存器件中具有很好的应用前景。从金属纳米晶存储器的工作原理、纳米晶的制备方法、以及新型介质材料和电荷俘获层结构等方面,对金属纳米晶存储器近年来的研究进展进行了总结。     

Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods

The Ge/Si nanocrystals on ultra thin high-k tunnel oxide Al2O3 were fabricated to form the charge trapping memory prototype with asymmetric tunnel barriers through combining the advanced atomic layer deposition (ALD) and pulse laser deposition (PLD)techniques. Charge storage characteristics in such memory structure have been investigated using capacitance-voltage (C-V) and capacitance-time (C-t) measurements. The results prove that both the two-layered and three-layered memory structures behave relatively qualified for the multi-level cell storage. The results also demonstrate that compared to electrons, holes reach a longer retention time even with an ultra thin tunnel oxide owing to the high band offset at the valence band between Ge and Si.     

Nonvolatile Charge Injection Memory Based on Black Phosphorous 2D Nanosheets for Charge Trapping and Active Channel Layers

2D van der Waals atomic crystal materials have great potential for use in future nanoscale electronic and optoelectronic applications owing to their unique properties such as a tunable energy band gap according to their thickness or number of layers. Recently, black phosphorous (BP) has attracted significant interest because it is a single‐component material like graphene and has high mobility, a direct band gap, and exhibits ambipolar transition behavior. This study reports on a charge injection memory field‐effect transistor on a glass substrate, where few‐layer BPs act as the active channel and charge trapping layers, and Al₂O₃ films grown by atomic layer deposition act as the tunneling and blocking layers. Because of the ambipolar properties of BP nanosheets, both electrons and holes are involved in the charge trapping process, resulting in bilateral threshold voltage shifts with a large memory window of 22 V. Finally, a memory circuit of a resistive‐load inverter is implemented that converts analog signals (current) to digital signals (voltage). Such a memory inverter also shows a clear memory window and distinct memory on/off switching characteristics.     

Electrical Characteristics of Memory Devices With a High- k HfO2 Trapping Layer and Dual SiO2/Si3N4 Tunneling Layer

A novel device structure with a high-k HfO₂ charge storage layer and dual tunneling layer (DTL) (SiO₂/Si₃N₄) is presented in this paper. Combining advantages of the high trapping efficiency of high-k materials and enhanced charge injection from the substrate through the DTL, the device achieves a fast program/erase speed and a large memory window. The device demonstrates excellent retention due to its physically thick DTL and also improved endurance without any increase of programming V_th throughout the cyclic test as compared with SONOS Flash memory devices using an Si₃N₄ trapping layer.     

Charge Trapping in Intergrain Regions of Pentacene Thin Film Transistors

A scanning Kelvin probe microscopy (SKPM) study of the surface potential of vacuum sublimed pentacene transistors under bias stress and its correlation with the film morphology is presented. While for thicker films there are some trapping centers inhomogeneously distributed over the film, as previously reported by other authors, by decreasing the film thickness the effect of thin intergrain regions (IGRs) becomes clear and a very good correlation between the topography and the potential data is observed. It is shown that in the thick pentacene grains the potential is homogeneous and independent of the gate bias applied with negligible charge trapping, while in the thin IGRs the potential varies with the applied gate bias, indicating that only an incomplete accumulation layer can be formed. Clear evidence for preferential charge trapping in the thin IGRs is obtained.     

Understanding Temperature‐Dependent Charge Extraction and Trapping in Perovskite Solar Cells

Understanding the factors that limit the performance of perovskite solar cells (PSCs) can be enriched by detailed temperature (T)‐dependent studies. Based on p‐i‐n type PSCs with prototype methylammonium lead triiodide (MAPbI₃) perovskite absorbers, T‐dependent photovoltaic properties are explored and negative T‐coefficients for the three device parameters (V_OC, J_SC, and FF) are observed within a wide low T‐range, leading to a maximum power conversion efficiency (PCE) of 21.4% with an impressive fill factor (FF) approaching 82% at 220 K. These T‐behaviors are explained by the enhanced interfacial charge transfer, reduced charge trapping with suppressed nonradiative recombination and narrowed optical bandgap at lower T. By comparing the T‐dependent device behaviors based on MAPbI₃ devices containing a PASP passivation layer, enhanced PCE at room temperature is observed but different tendencies showing attenuating T‐dependencies of J_SC and FF, which eventually leads to nearly T‐invariable PCEs. These results indicate that charge extraction with the utilized all‐organic charge transporting layers is not a limiting factor for low‐T device operation, meanwhile the trap passivation layer of choice can play a role in the T‐dependent photovoltaic properties and thus needs to be considered for PSCs operating in a temperature‐variable environment.     

Doping‐Induced Charge Trapping in Organic Light‐Emitting Devices

By using pyran‐containing donor–acceptor dyes as doping molecules in organic light‐emitting devices (OLEDs), we scrutinize the effects of charge trapping and polarization induced by the guest molecules in the electro‐active host material. Laser dyes 4‐(dicyanomethylene)‐2‐methyl‐6‐[2‐(julolidin‐9‐yl)phenyl]ethenyl]‐4H‐pyran (DCM2) and the novel 4‐(dicyanomethylene)‐2‐methyl‐6‐{2‐[(4‐diphenylamino)phenyl]ethenyl}‐4H‐pyran (DCM‐TPA) are used as model compounds. The emission color of these polar dyes depends strongly on doping concentration, which we have attributed to polarization effects induced by the doping molecules themselves. Their frontier orbital energy levels are situated within the bandgap of the tris(8‐hydroxyquinoline)aluminum (Alq₃) host matrix and allow the investigation of either electron trapping or both electron and hole trapping. In the case of DCM‐TPA doping, we were able to show that electron trapping leads to a partial shift of the recombination zone out of the doped Alq₃ region. To impede charge‐recombination processes taking place in the undoped host matrix, a charge‐blocking layer efficiently confines the recombination zone inside the doped zone and gives rise to increased luminous efficiency. For a doping concentration of 1 wt.‐% we obtain a maximum luminous efficiency of 10.4 cd A^–1. At this doping concentration, the yellow emission spectrum shows excellent color saturation with CIE chromaticity coordinates x, y of 0.49 and 0.50, respectively. In the case of DCM2 the recombination zone is much less affected for the same doping concentrations, which is ascribed to the fact that both electrons and holes are being trapped. The experimental findings are corroborated with a numerical simulation of the doped multilayer devices.     

Decoupling the Bias‐Stress‐Induced Charge Trapping in Semiconductors and Gate‐Dielectrics of Organic Transistors Using a Double Stretched‐Exponential Formula

A novel strategy for analyzing bias‐stress effects in organic field‐effect transistors (OFETs) based on a four‐parameter double stretched‐exponential formula is reported. The formula is obtained by modifying a traditional single stretched‐exponential expression comprising two parameters (a characteristic time and a stretched‐exponential factor) that describe the bias‐stress effects. The expression yields two characteristic times and two stretched‐exponential factors, thereby separating out the contributions due to charge trapping events in the semiconductor layer‐side of the interface and the gate‐dielectric layer‐side of the interface. The validity of this method was tested by designing two model systems in which the physical properties of the semiconductor layer and the gate‐dielectric layer were varied systematically. It was found that the gate‐dielectric layer, in general, plays a more critical role than the semiconductor layer in the bias‐stress effects, possibly due to the wider distribution of the activation energy for charge trapping. Furthermore, the presence of a self‐assembled monolayer further widens the distribution of the activation energy for charge trapping in gate‐dielectric layer‐side of the interface and causes the channel current to decay rapidly in the early stages. The novel analysis method presented here enhances our understanding of charge trapping and provides rational guidelines for developing efficient OFETs with high performance.