高压RESURF LDMOSFET的实现

利用ＲＥＳＵＲＦ技术，使用常规低压集成电路工艺，实现了适用于ＨＶＩＣ、耐压达１０００Ｖ的ＬＤＭＯＳＦＥＴ。本文介绍了该高压ＬＥＭＯＳＦＥＴ的设计方法、器件结构、制造工艺测试结果，此外，本文还从实验和分析的角度探讨了覆盖在漂移区上面的金属栅－金属栅场板长度ＬＦ对ＲＥＳＵＲＦ器件耐压的影响。     

GaAs MESFET大信号瞬态模拟

本文采用了大信号瞬态分析方法，从砷化镓（ＧａＡｓ）材料参数和器件几何参数出发，通过求解Ｐｏｉｓｓｉｏｎ方程和连续性方程，模拟出ＦＥＴ器件端口特性，得到了大小信号器件模型不同的定量依据，并在此基础上提取出了ＦＥＴ非线性模型参数．本文所开发的软件，其有效性在从材料器件物理参数出发，一步设计出微波单片集成电路（ＭＭＩＣ）的ＣＡＤ过程中得到了验证．     

GaAs IC CAD方法

本文重点论述ＧａＡｓ ＩＣ ＣＡＤ方法，包括：精确的ＧａＡｓ ＭＥｓＦＥＴ、ＨＥＭＴ和ＨＢＴ等有源器件模型；大、小信号模型参数提取；噪声模型；成品优化；高频、高速微带传输线模型；电路模拟与优化；砷化镓门阵等。还评述了ＧａＡｓ ＩＣ ＣＡＤ集成软件包及进一步工作。     

深亚微米MOSFET模型研究进展

文中对在深亚微米ＭＯＳＦＥＴ的器件模型研究基础上，提出了研究ＭＯＳＦＥＴ模型值得注意的问题，并对如何建立深亚微米ＭＯＳＦＥＴ模型作出了有益的探讨。     

FET器件寄生元件的剥离技术

介绍了一种晶片条件下ＦＥＴ器件（包括ＭＯＳＦＥＴ，ＧａＡｓＭＥＳＦＥＴ和ＨＥＭＴ）寄生元件的剥离技术，并利用此技术获取了器件的本征［Ｙ］参数。     

双栅MOSFET的研究与发展

具有特殊结构的双栅ＭＯＳＦＥＴ是一种高速度、低功耗ＭＯＳＦＥＴ器件,符合未来集成电路发展的方向。文章介绍了多种双栅ＭＯＳＦＥＴ的结构、优点,以及近年来国内外对双栅ＭＯＳＦＥＴ的研究成果。     

GaAs MESRET平面型变容管高频特性分析

本文分析用于ＧａＡｓ ＭＭＩＣ调频器件ＭＥＳＦＥＴ平面型变容管的微波特性,讨论了器件几何结构与直流参数,Ｓ参数之间的关系,重点研究了器件串联电阻对微波特性的影响,给出了变容管变电容比与器件几何尺寸。     

有机薄膜电致发光的回顾和展望

综述了有机薄膜电致发光（ＯＴＦＥＬ）的发展过程，总结了ＯＴＦＥＬ的四种器件结构和工作原理，介绍了器件的制备并了选择有机发光材料的基本原则，文末展望了ＯＴＦＥＬ的应用前景。     

FLOTOX EEPROM存储管的简单模型分析和实验研究

分析了ＦＬＯＴＯＸ ＥＥＰＲＯＭ的简单电路模型和擦写特性。实验研究了不同的器件结构参数和擦写脉冲对存储管特性的影响，表明隧道氧化层和多晶之间介质层的厚度对ＥＥＰＲＯＭ阈会晤窗口有很大的影响、采用指数上升波形或三角波形进行了编程可以改善ＥＥＰＲＯＭ的耐久性。     

具有隐埋电镀热沉结构用于高性能MMIC的大功率GaAs FET

报道了一种称作“先进的ＳＩＶＦＥＴ”的ＦＥＴ结构（先进的源区通孔ＦＥＴ）。“ＳＩＶＦＥＴ”（源区通孔ＦＥＴ）是一种新型的ＦＥＴ，其每个源电极都通过通孔与４０μｍ厚的背面电镀热沉金属相连接地，以达到减小源寄生电感的目的。为了获得低的热阻，芯片厚度要小达３０μｍ。“先进的ＳＩＶＦＥＴ”的改进结构包含了一种选择隐埋ＰＨＳ（电镀热沉）用以代替背面的厚金层。在这种ＦＥＴ中，由于有源层在器件工作时会产生热量，     

IEEE802.15.4协议的性能分析与仿真

IEEE 802.15.4是一个自组织的无线网络标准,其中制定了PHY层和MAC层规范,主要应用场合为低成本、低功耗、低复杂度的无线个域网.许多参数在IEEE 802.15.4标准中仅给出取值范围而并未给出确定的值,虽然这些值对系统性能有着较为显著的影响.个域网中的设备大量采用电池供电,因此实现更低的能量消耗是该网络标...     

Characteristics of double-gate SOI CMOS nanotransistors for promising technologies with a low power consumption level

A procedure, allowing one to optimize topological and electrophysical parameters of double gate SOI nanotransistors with a thin unalloyed working area, with underlap gate and drain/source regions with regard to the physical restrictions and process requirements, without recourse to the 2D-simulation, is considered. Based on the numerical simulation results, the selection criteria of the key topological parameters of transistors for implementing the requirements in accordance with the International Technology Roadmap for Semiconductor 2010 Edition program for promising applications with a low power consumption level are discussed. The complex analysis of the VACs of transistors and gate characteristics, such as a time switching delay, as well as active and static power, shows that prototypes of the considered units are applicable for implementing high-performance VLSI projects.     

NB-IoT功控方式和低功耗技术分析

蜂窝物联网NB-IoT是目前运营商的重点建设网络,其发展前景和应用需求也在不断扩大,其中,低功耗是NB-IoT最重要的技术特点之一,是促进网络和应用发展的重要因素。本文在介绍NB-IoT网络结构、主要技术的基础上,重点介绍NB-IoT的功控方式及如何实现低功耗,并分析其中的影响因素和参数,对NB网络功控方面提出建议。     

Interconnect-based system-level energy and power prediction to guide architecture exploration

We present a novel technique to predict energy and power consumption in an electronic system, given its behavioral specification and library components. The early prediction gives circuit designers the freedom to make numerous high-level choices (such as die size, package type, and latency of the pipeline) with confidence that the final implementation will meet power and energy as well as cost and performance constraints. Our unique statistical estimation technique associates low-level, technology dependent physical and electrical parameters, with expected circuit resources and interconnect. Further correlations with switching activity yield accurate results consistent with implementations. All feasible designs are investigated using this technique and the designer may tradeoff between small size, high speed, low energy, and low power. The results for designs of two popular signal processing applications, predicted prior to synthesis, are within 10% accuracy of power estimates performed on synthesized layouts.     

Test results for on-board burst-mode CQPSK modem

An on-board burst-mode modem for coherent processing of a QPSK signal at 120 Mb/s is realized with small, low mass and low power consumption. This paper presents the hardware configuration and the various measured test data including physical characteristics. The overall performance through an earth station modem is also presented.     

Impact of interface impurities on heterostructure field-effecttransistors

The influence of C and Si impurities at the substrate/epitaxy interface on the threshold voltage of GaAs/AlGaAs selectively doped heterostructure transistors has been investigated both experimentally and theoretically using a one-dimensional simulation. The presence of C raises the conduction band relative to the Fermi level and reduces the electron density in the channel. This results in a positive shift of the depletion-mode (DFET) threshold voltage as the interfacial C concentration increases. For low C concentrations the DFET threshold voltage decreases with increasing Si at the interface. The impact of interfacial C and Si is small on the enhancement-mode (EFET) threshold voltage     

Power consumption of multiplexed liquid-crystal displays

Display power consumption is calculated as a function of the physical display parameters for a five-voltage, line-at-a-time drive scheme. It is found that at high multiplexing levels the power varies as the product of the number of columns and the square of the number of rows, assuming that the rows are strobed. Typical power for a small 128 character display multiplexed at 1/28 duty cycle is expected to be 140 µW.     

Mathematical Characterization and Simulation of LoRa

Wireless Personal Communications - LoRa is a recently developed physical layer modulation technique characterized by low power consumption and long range communication capabilities. Due to the...     

Flexible Prime‐Field Genus 2 Hyperelliptic Curve Cryptography Processor with Low Power Consumption and Uniform Power Draw

This paper presents an energy‐efficient (low power) prime‐field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a 0.13 μm standard CMOS technology, performs an 81‐bit divisor multiplication in 503 ms consuming only 6.55 μJ of energy (average power consumption is 12.76 μW). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.     

双极型LDO线性稳压器的设计

在使用电池供电的产品中,两个很关键的设计就是低漏失电压Vdropout和低静态功耗,Vdropout能保证电池使用效率高,低静态功耗能保证电池使用时间长,LDO线性稳压器也不例外。主要针对这两个特性加上能控制开关和过流过温保护等功能,设计并实现了一款双极型LDO线性稳压器。采用SA-5V工艺中特有的横向pnp管做调整管,使得调整管集电极寄生电阻RC只有10Ω,工艺流片后测试线性调整率为5 mV,负载调整率为14 mV,最大输出电流为30 mA,最小漏失电压为280 mV,在频率为20 Hz～50 kHz输出噪声为80μVRMS,具有良好的应用前景,可适合大规模批量生产。