Fully differential optoelectronic integrated receiver implemented by 0.35μm standard CMOS process

A high-bandwidth, high-sensitivity fully differential optoelectronic integrated receiver is implemented in a chartered 3.3 V standard 0.35μm analbg CMOS process. To convert the incident light into a pair of fully differential photo-currents, a novel fully differential photodetector is proposed, which is composed of two completely identical photodiodes. The mea- surement results show that the receiver achieves a 1.11 GHz 3 dB bandwidth and a -13 dBm sensitivity for a 10-12 bit error at 1.5 Gb/s data rate under illumination by 850 nm incident lights.     

Fully differential optoelectronic integrated receiver imple-mented by 0.35 μm standard CMOS process

A high-bandwidth, high-sensitivity fully differential optoelectronic integrated receiver is implemented in a chartered 3.3 Vstandard 0.35 um analog CMOS process. To convert the incident light into a pair of fully differential photo-currents, anovel fully differential photodetector is proposed, which is composed of two completely identical photodiodes. The mea-surement results show that the receiver achieves a 1.11 GHz 3 dB bandwidth and a -13 dBm sensitivity for a 10-12 bit error at1.5 Gb/s data rate under illumination by 850 nm incident lights.     

一种与标准CMOS工艺兼容的光电集成接收机设计与实现

设计了一种与标准CMOS工艺完全兼容的高速光电探测器和宽带光电集成接收机,并采用0.6μm标准CMOS工艺流片. 测试结果表明,该光电集成接收机的性能已接近实用要求. 探测器的频率响应带宽为1.11GHz,光电集成接收机的3dB带宽为733MHz;在误码率为10-12条件下,对波长为850nm的输入光信号,灵敏度达到-9dBm.     

高速12路并行CMOS单片光电集成接收机设计与实现

设计并实现了一个高速12路并行CMOS单片光电集成接收机.其每一路都包括一个光探测器、一个跨阻放大器以及后续放大电路.双光电二极管(DPD)结构可以提高接收机速度,但同时降低了响应度.在跨阻放大器电路中采用有源电感来展宽-3dB带宽.通过无锡上华(CSMC)0.6μm CMOS工艺流片并对芯片进行了测试.测试结果显示该接收机单路传输比特率可达0.8～1.4 Gb/s,总的12路可传输15Gb/s数据.     

可应用于光互连的新型高带宽、高灵敏度差分光接收机的概念提出与设计

提出了一种可应用于高速光通信和光互连的新型高带宽、高灵敏度差分光接收机.其中,高带宽和高灵敏度分别通过输入负载平衡的全差分跨阻前置放大器和将入射光信号转换成一对差分光生电流信号的两个光电探测器来实现.与常用光接收机相比,这种新型光接收机无任何附加成本.设计了一种相应的、与0.35μm标准CMOS工艺完全兼容的光电集成接收机.其中,光电探测器采用面积为60μm×30μm、结电容为1.483pF的插指型p+/n-well/p-substrate光电二极管.仿真结果表明:该光电集成接收机的带宽为1.37GHz;跨阻增益为81.9dBΩ;面积为0.198mm2;数据传输率至少可达2Gb/s;对于215-1位的输入伪随机码序列(PRBS),在误码率为10-12条件下,灵敏度至少可达-13dBm.     

A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications

This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz.     

一种新颖全差分光电集成接收机的标准CMOS实现

提出一种新颖的全差分光电集成接收机,它包含了全差分光电探测器和相应的差分接收电路,其中全差分光电探测器的作用是实现入射光信号到全差分光生电流信号的转换.采用特许3.3 V、0.35μm标准CMOS工艺,实现了一种相应的宽带、高灵敏度全差分光电集成接收机.测试结果表明:对于850 nm的入射光,集成全差分光电探测器的差分跨阻前置放大器(TIA)的工作速率可达到500 Mbit/s,而整个光接收机的带宽则达到了1.098 5 GHz;在10-12的误码率条件下,灵敏度可达到-12.3 dBm.     

A 0.5-8.5 GHz fully differential CMOS distributed amplifier

A fully integrated fully differential distributed amplifier with 5.5 dB pass-band gain and 8.5 GHz unity-gain bandwidth is described. The fully differential CMOS circuit topology yields wider bandwidth than its single-ended counterpart, by eliminating the source degeneration effects of parasitic interconnect, bond wire, and package inductors. A simulated annealing CAD tool underpins the parasitic-aware methodology used to optimize the design including all on-chip active and passive device and off-chip package parasitics. Mixed-mode S-parameter measurement techniques used for fully differential circuit testing are reviewed. Integrated in 1.3/spl times/2.2 mm/sup 2/ in a standard 0.6 /spl mu/m CMOS process, the distributed amplifier dissipates 216 mW from a single 3 V supply.     

A Fully Integrated 60GHz Four Channel CMOS Receiver with 7GHz Ultra-Wide Bandwidth for IEEE 802.11ad Standard

In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

1.3 μm monolithic integrated optoelectronic receiver using anInGaAs MSM photodiode and AlGaAs/GaAs HEMTs grown on GaAs

The first 1.3 μm monolithic integrated optoelectronic receiver using an InGaAs MSM photodiode and AlGaAs/GaAs HEMTs grown on a GaAs substrate has been fabricated. At differential output of the implemented multistage amplifier the transimpedance is 26.8 kΩ (into 50 Ω). The bandwidth of 430 MHz implies suitability for transmission rates up to 622 Mbit/s     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

A 270 MHz, 1 Vpk-pk, Low-Distortion Variable Gain Amplifier in a 0.35 μm CMOS Process

A fully balanced CMOS Variable Gain Amplifier (VGA) based on current-mode techniques suitable for high frequency applications and large signals is presented. The VGA consists of an analog multiplier, current gain stages, and resistive loads. A frequency compensation scheme based on a capacitive feed-forward technique increases the bandwidth by more than 60%. Common-Mode Feed-Forward (CMFF) techniques are used to minimize dc offsets. The gain can be programmed from 0 to 42 dB with ?3 dB bandwidth greater than 270 MHz; a gain calibration scheme for precise gain control applications is included. The Third Harmonic Distortion (HD3) is less than ?55 dB for differential input and output voltages of 1 V_pk-pk. The VGA was fabricated in a standard 0.35 μm CMOS process, and consumes around 54 mW from a single power supply of 2.7 V.     

A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10~(-9). The chip dissipates 60 mW under a single 3.3 V supply.     

A complete 400-Mb/s burst-mode data OEIC receiver

A fully integrated burst-mode GaAs MESFET optoelectronic integrated circuit (OEIC) receiver, 215 mil×109 mil, that has been designed and implemented for point-to-point data links for application as a phased-array antenna controller is described. The chip provides a low-cost means for passing 400-Mb/s antenna control information using fiber optics with a very low bit-error rate (BER). Approximately 350 source-coupled FET logic gates are present on the chip. A new data coding and timing recovery scheme that is highly tolerant to jitter over a wide bandwidth has been developed. The OEIC uses an on-chip metal-semiconductor-metal (MSM) photodiode with 0.12-A/W responsivity measured at 780 nm and was fabricated in a 1.0-mm GaAs MESFET manufacturing technology. The low capacitance semi-insulating GaAs substrate minimizes the coupling between analog and digital circuitry. The circuit operates from a single 5-V supply, consumes 1 W of power, and provides an 8-b CMOS output bus together with various utility flags. Optical sensitivity is estimated at -20 dBm for 10^-14 BER     

Integrated optical receiver with beam localisation

The performance of optical receivers is degraded by misalignment and defocusing of the incident light beam on a detector. The presented integrated optical receiver solves the alignment and defocusing problem using optoelectronic light beam localisation. A demonstrator is realised in a standard CMOS technology     

Integrated CMOS amplifier for ENG signal recording

The development and in vivo test of a fully integrated differential CMOS amplifier, implemented with standard 0.7-microm CMOS technology (one poly, two metals, self aligned twin-well CMOS process) intended to record extracellular neural signals is described. In order to minimize the flicker noise generated by the CMOS circuitry, a chopper technique has been chosen. The fabricated amplifier has a gain of 74 dB, a bandwidth of 3 kHz, an input noise of 6.6 nV/(Hz)0.5, a power dissipation of 1.3 mW, and the active area is 2.7 mm2. An ac coupling has been used to adapt the electrode to the amplifier circuitry for the in vivo testing. Compound muscle action potentials, motor unit action potentials, and compound nerve action potentials have been recorded in acute experiments with rats, in order to validate the amplifier.     

A 60–110 GHz Transmission-Line Integrated SPDT Switch in 90 nm CMOS Technology

This letter demonstrates a fully integrated transmit/receive single-pole-double-throw switch in standard bulk 90 nm CMOS process. This switch is based on the transmission-line integrated approach that reduces the effect of parasitic capacitance of transistors in the desired band, and this approach can achieve good isolation and return loss with fewer stages of transistors and broad bandwidth. The switch provides an insertion loss of 3–4 dB and a return loss better than 10 dB in 60–110 GHz. The measured isolation is better than 25 dB. The measured 1 dB compression point of input power is 10.5 dBm at 75 GHz. To the best of our knowledge, this is the first CMOS switch operating beyond 100 GHz.      

Scaleable CMOS Current-Mode Preamplifier Design for an Optical Receiver

We have designed a process-insensitive preamplifierfor an optical receiver, fabricated it in several different minimumfeature sizes of standard digital CMOS, and demonstrated designscaleability of this analog integrated circuit design. The sameamplifier was fabricated in a 1.2 µm and two different0.8 µm processes through the MOSIS foundry [1].The amplifier uses a multi-stage, low-gain-per-stage approach.It has a total of 5 identical cascaded stages. Each stage isessentially a current mirror with a current gain of 3. Threeof these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with anInGaAs MSM detector by using a thin-film epilayer device separationand bonding technology [2]. This quasi-monolithic front-end of anoptical receiver virtually eliminates the parasitics between thephotodetector and the silicon CMOS preamplifier. We have demonstratedspeed and power dissipation improvement as the minimum feature sizeof the transistors shrink.     

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.