Temperature and electric field characteristics of time-dependentdielectric breakdown for silicon dioxide and reoxidized-nitrided oxides

TDDB characteristics of 150 Å reoxidized nitrided oxide (ONO) gate dielectrics were examined at temperatures from 77 K to 400 K. These ONO films were processed with different conditions of rapid thermal nitridation (RTN) and rapid thermal re-oxidation (RTO). Optimized ONO films show better Q_bd performance while maintaining a similar temperature and electric field dependence compared to SiO₂. The low temperature activation energy for ONO and SiO₂ is found to be strongly temperature dependent, and the charge to breakdown, Q_bd, is closely related to the electron trap generation/trapping rate rather than the amount of hole trapping for high field stress. To further verify the effect of hole trapping on TDDB, X-ray irradiation was applied to wafers at different process steps. The results clearly show that the amount of hole trapping does not correlate with the charge to breakdown     

The use of ultrathin reoxidized nitrided gate oxide for suppressionof boron penetration in BF2+-implanted polysilicongated p-MOSFETs

The authors report the use of rapid thermal reoxidized nitrided thin (~90-Å) gate oxides in BF₂⁺-implanted polysilicon gated p-MOSFETs. Although lightly nitrided gate oxides are unable to block the boron penetration, reoxidized nitrided gate oxides are found to have excellent barrier properties against boron penetration. In addition, excellent electrical characteristics in terms of device subthreshold conduction and transconductance are illustrated     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

High-field mobility effects in reoxidized nitrided oxide (ONO)transistors

The high-field mobility behavior of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room temperature and 77 K on both n- an p-channel FETs, for both ONO and conventional SiO ₂ films. While the peak electron mobility is much higher for standard SiO₂, a crossover occurs in the high-field region beyond which ONO transistors exhibit higher mobility. The crossover voltage is reduced at 77 K. Measurements intended to gain further insight into this phenomenon suggest that differences in surface roughness scattering, or the buried-channel nature of an ONO NMOS transistor, are the most likely explanations for the high-field mobility behavior observed     

Thin gate and analog capacitor dielectrics for submicron device fabrication

The miniaturization of devices in ULSI circuits are accompanied by shrinking vertical, as well as horizontal, device parameters such as junction depth, lateral impurity diffusion and film thicknesses. This is achieved by decoupling process steps,i.e. processing at a reduced thermal budget. However, as device dimensions decrease, greater demand in transistor noise immunity and reliability may not be achievable with low-temperature (<900° C) oxidation processes. Low temperature CVD ONO (oxide-nitride-oxide) dielectrics have been evaluated for applications in ULSI gate as well as capacitor structures. Time dependent dielectric breakdown data have shown that ONO has longer lifetime than thermal oxide of equivalent thickness. Such stacked dielectrics nevertheless result in complex processing steps. With the advances in rapid thermal processing equipment today, rapid thermal oxide (RTO) has been shown to offer potential benefits of high temperature without significant addition to the overall thermal budget. We have shown that transistors with RTO gate oxides exhibit longer lifetime and lower noise compared to those with furnace grown gate oxides. We have also shown that interpoly RTO oxides have remarkable dielectric strength of >8 MV/cm. For enhanced radiation hardness and impurity masking capability as well as higher permittivity, rapid thermal nitrided oxides may be a potential choice deserving further evaluation. These nitrided oxides must be reoxidized to reduce densities of interface states and electron traps created during the nitridation process.     

Gate bias polarity dependence of charge trapping and time-dependentdielectric breakdown in nitrided and reoxidized nitrided oxides

The gate bias polarity dependence of charge trapping and time-dependent dielectric breakdown (TDDB) in nitrided and reoxidized nitrided silicon dioxides prepared by rapid thermal processing (RTP) is reported. Charge trapping during high-field injection can be reduced by rapid thermal nitridation for both substrate and gate injection. While reoxidation of nitrided oxides shows further reduction in charge trapping for substrate injection, degradation is observed for gate injection. Similar effects are observed for TDDB: reoxidized nitrided oxides show charge-to-breakdown in excess of 300 C/cm² for substrate injection, but less than 30 C/cm² for gate injection. These effects are related to the nitrogen and hydrogen profiles in the oxides. By tailoring the process conditions, a symmetric behavior of NO and RONO films with low charge trappings and Q _BD in excess of 50 C/cm² is possible, making them attractive as long-lifetime dielectrics from EEPROM (electrically erasable programmable ROM) and flash EEPROM technologies     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

Electrical properties of MOSFET's with N2O-nitridedLPCVD SiO2 gate dielectrics

Electrical properties of MOSFETs with gate dielectrics of low-pressure chemical-vapor-deposited (LPCVD) SiO₂ nitrided in N₂O ambient are compared to those with control thermal gate oxide. N₂O nitridation of CVD oxide, combines the advantages of interfacial oxynitride growth and the defectless nature of CVD oxide. As a result, devices with N₂O-nitrided CVD oxide show considerably enhanced performance (higher effective electron mobility), improved reliability (reduced charge trapping, interface state generation, and transconductance degradation), and better time-dependent dielectric breakdown (TDDB) properties (t_BD ) compared to devices with control thermal oxide     

High-temperature rapid thermal nitridation of silicon dioxide for future VLSI applications

The use of nitrided SiO2for very large scale integration (VLSI) applications is becoming increasingly attractive. Nitridation can convert a thin surface region of SiO2into a nitroxide film which is a diffusion barrier that allows the use of thin dielectrics in MOS structures and a variety of gate metals without contaminating the interfacial region. We propose a two-activation-energy model of nitridation and suggest a structure for MOS gate insulator applications. We achieved this structure using rapid thermal nitridation at 1300°C for 20 s in 1 atm. of ammonia.     

Low-temperature furnace-grown reoxidized nitrided oxide gatedielectrics as a barrier to boron penetration

Reoxidized nitrided oxide (ROXNOX) gate dielectrics can be used to block the diffusion of boron into the MOS channel region. However, fixed oxide charge annealing can mask the effects of boron in the channel, a particularly important consideration for low-temperature gate oxides. The authors separate the effect of fixed charge annealing from the effect of boron diffusion and demonstrate that a low-temperature furnace-grown reoxidized nitrided oxide has a substantial advantage over conventional gate oxides in protecting the channel from boron over a wide range of annealing times and temperatures. They also address the issue of fixed charge annealing in low-temperature reoxidized nitrided oxides and present an approach to maintain acceptable gate dielectric quality while preserving a low D-t product for integration into a scaled dual-gate CMOS process     

A comprehensive study of suppression of boron penetration byamorphous-Si gate in P+-gate PMOS devices

This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p⁺-gate devices. The characteristics and reliability for different gate structures (poly-Si, α-Si, poly-Si/poly-Si, poly-Si/α-Si, α-Si/poly-Si, and α-Si/α-Si) in p ⁺ polygate PMOS devices are investigated in detail. The suppression of boron penetration by the nitrided gate oxide is also discussed. The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p⁺ polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate. Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance. The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p⁺-gate PMOS device for future dual-gate CMOS process. In addition, by employing a long time annealing at 600°C prior to p⁺-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate. Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect     

Gate engineering for deep-submicron CMOS transistors

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET's. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET's is investigated. The suppression of boron penetration is confirmed by the SIMS profiles, and is attributed mainly to the diffusion retardation effect in bulk polysilicon by the presence of nitrogen. The MOSFET' I-V characteristics, MOS capacitor quasi-static C-V curves, SIMS profiles, gate sheet resistance, and oxide Q_bd are compared for different nitrogen implant conditions. A nitrogen dose of 5×10¹⁵ cm^-2 is found to be the optimum choice at an implant energy of 40 keV in terms of the overall electrical behavior of CMOSFET's. Under optimum design, gate nitrogen implantation is found to be effective in eliminating boron penetration without degrading performance of either p⁺ gate p-MOSFET and n⁺ gate n-MOSFET. Secondly, the impact of gate microstructure on the performance of deep-submicron CMOSFET's is discussed by comparing poly and amorphous silicon gate deposition technologies. Thirdly, poly-Si_1-xGe_x is presented as a superior alternative gate material. Higher dopant activation efficiently results in higher active-dopant concentration near the gate/SiO₂ interface without increasing the gross dopant concentration. This plus the lower annealing temperature suppress the dopant penetration. Phosphorus-implanted poly-Si_1-xGe_x is gate is compared with polysilicon gate in this study     

Improvement in threshold voltage control by minimizing boronpenetration in a LV-GCMOS technology

Maintaining tight threshold voltage (V_T) control for a low-voltage CMOS process is critical due to the large impact of V_T on circuit performance at low power supply voltages. In this paper, PMOS V_T was shown to be sensitive to poly gate thickness and BF₂⁺ source/drain implant energy. This data helped identify boron penetration as a prime contributor to PMOS threshold voltage variation. SIMS measurements were used to investigate boron diffusion through the poly gate at various stages in the process flow. These SIMS profiles pointed to the low-temperature thermal cycle of the nitride spacer deposition as a key step which influenced the amount of boron penetration and thus the final device threshold voltage. Experimental evidence shows that the temperature gradient across the nitride spacer deposition furnace causes a variable amount of boron penetration resulting in a large variation in PMOS V_T. We adopted a process flow change which virtually eliminated boron penetration and significantly reduced the sensitivity of the devices to manufacturing variations. Threshold voltage variation was reduced by a factor of two     

Thickness dependence of boron penetration through O2 and N2O-grown gate oxides and its impact on threshold voltagevariation

We report on a quantitative study of boron penetration from p⁺ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O₂ or N₂O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model to predict the magnitude of boron penetration, N_B, for thicknesses other than those measured. We find that the minimum t_ox required to inhibit boron penetration is always 2-4 nm less when N₂O-grown gate oxides are used in place of O₂- grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in ULSI technologies. Because of the strong dependence of boron penetration on t_ox, incremental variations in oxide thickness result in a large variation in N_B , leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 10¹¹ cm^-2     

Effect of Nitrogen on the Frequency Dependence of Dynamic NBTI-Induced Threshold-Voltage Shift of the Ultrathin Oxynitride Gate P-MOSFET

The dynamic negative-bias-temperature-instability- induced threshold-voltage shift |DeltaV_t| of p-MOSFETs employing ultrathin decoupled-plasma- and thermal-nitrided SiO₂ gate dielectrics is studied as a function of gate frequency. The dependence of |DeltaV_t| on the gate frequency under unipolar stress is observed to become weaker for p-MOSFETs having higher nitrogen concentrations in the gate oxide. Evidence shows that reduced frequency dependence results from a greater lock-in of |DeltaV_t|, mainly due to an increased generation of recovery-resistant deep-level hole traps in the heavily nitrided gate p-MOSFET.     

Nitridation and post-nitridation anneals of SiO2 forultrathin dielectrics

A technique of post-oxidation annealing to improve the properties and long-term reliability of ultrathin (<100 Å) MOS gate dielectrics is discussed. In this technique, after oxidation, nitridation is done in NH₃, followed by a light reoxidation in O₂, and then an inert anneal in Ar or N₂. Using this technique, both optimum performance and reliability can be obtained without sacrificing either. NH₃ anneal of SiO₂ improved the hot-electron immunity, but degraded the interface quality. Good properties could be obtained by a strong reoxidation of the nitrided films, at the expense, however, of a substantial increase in the film thickness. Nitrogen and argon ambients were found to be equally effective at improving film properties. By annealing the film in an inert ambient following reoxidation of the nitroxide, fixed charge can be further decreased with little oxide grown, electron mobility in NMOS FETs increases further, and the hot-electron lifetime is much longer than that of the starting oxide     

Study of low-frequency charge pumping on thin stacked dielectrics

The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO₂ dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO₂ dielectrics to thin stacked gate dielectrics are discussed     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature