非对称轻掺杂漏(LDD)MOSFET

提出并制作了一种仅有漏端轻掺杂区的MOSFET新结构──非对称LDD MOSFET。它与通常LDD MOSFET相比,抑制热载流子效应的能力相同,源漏串联电阻降低40％左右,线性区和饱和区的跨导分别增加50％和20％左右。用该器件制作的CMOS电路,其速度性能优于通常LDD MOSFET制作的同样电路。     

SiO_2边墙技术及在LDD MOSFET中的应用

<正> 一、引言 在MOSFET研究发展中,轻掺杂漏(LDD)MOSFET和自对准MOSFET已越来越引人注目。这两种MOSFET制造中,边墙的形成是关键。如何精确控制边墙宽度是控制轻掺杂漏长度的基础,而控制边墙的高度和宽度则对自对准硅化钛MOSFET中的栅与漏—源区硅化钛电极的隔离十分重要。此外,边墙技术还可应用于形成亚微米栅以取代掩膜形成栅。本文介绍了一种形成一定高度和宽度的SiO_2边墙的方法。     

基于0.13μm工艺的1.5V低功耗MOSFET器件设计

针对0.13μm工艺常规MOSFET器件的制备流程进行了分析,提出了低功耗工艺改善方法,并针对优化工艺条件下的器件进行TCAD仿真,设计并进行了完整的DOE实验及样品性能测试。测试结果表明,通过调整轻掺杂漏区(LDD)的离子注入条件,冠状离子注入区的角度、浓度以及沟道阀值电压离子注入区浓度等一系列方法,实现了0.13μm工艺1.5 V MOSFET器件关断条件下漏电流低于1 pA/μm。     

LDD功率器件表面电场解析模型及优化

提出低掺杂漏(Lightly Doped Drain,LDD)功率器件表面电场和电势解析模型。基于分区求解二维Poisson方程,获得二维表面电场和电势的解析表达式。借助此模型,研究器件结构参数对表面电场和电势的影响;计算漂移区长度与击穿电压的关系,分析了击穿电压随低掺杂漏区掺杂浓度和漂移区厚度的变化,从理论上揭示了获得最大击穿电压的条件。解析结果与数值结果吻合较好,验证了模型的准确性,该模型可用于硅基LDD功率器件的设计优化。     

包含衬底电流的LDD MOSFET输出I-V特性的经验模型分析

采用双曲正切函数的经验描述方法和器件物理分析方法,建立了适用于亚微米、深亚微米的LDD MOSFET输出I-V特性解析模型,模型中重点考虑了衬底电流的作用.模拟结果与实验有很好的一致性.该解析模型计算简便,对小尺寸器件中的热载流子效应等能够提供较清晰的理论描述,因此适用于器件的优化设计及可靠性分析.     

适用于VLSI CAD的非均匀掺杂小尺寸MOSFET阈值电压模型

本文讨论了目前使用的MOSFET阈值电压模型的局限性,尝试了用分段近似法求解非均匀掺杂MOSFET的阈值电压,在此基础上提出了一个新的模型公式.它能反映非均匀掺杂MOSFET 阈值电压衬偏特性;不仅适用于浅注入,而且适用于深注入情况;不仅适用于长沟道,而且适用于小尺寸器件.此模型的计算结果同数值分析器MINIMOS的有关计算值相比,符合得很好.该模型公式特别适用于 VLSI CAD.     

一种新的有沟道注入的短沟MOSFET的阈电压解析模型

本文提出一个非均匀掺杂、短沟道MOSFET阈电压的准二维解析模型。用此模型对各种不同条件下的微米、亚微米MOSFET的阈电压进行了计算,其结果与二维数值分析程序得到的结果相符甚好。本模型可用于电路分析程序,工艺容错分析及器件的优化设计。     

一种适用于短沟道LDD MOSFET参数提取的改进方法

提出了一种适用于短沟道LDD MOSFET的改进型参数提取方法,通过对栅偏压范围细分后采用线性回归方法,提取偏压相关参数,保证了线性回归方法的精度和有效性,避免了对栅偏压范围的优化和误差考虑.提取出的参数用于已建立的深亚微米LDD MOSFET的I-V特性模型中,模拟与测试数据的吻合表明了该方法的实用性.     

双栅肖特基源漏MOSFET的阈值电压模型

通过求解泊松方程得到了双栅肖特基势垒MOSFET的解析模型. 这个解析模型包括整个沟道的准二维电势分布和适用于短沟双栅肖特基势垒MOSFET的阈值电压模型.数值模拟器ISE DESSIS验证了模型结果.     

双栅肖特基源漏MOSFET的阈值电压模型

通过求解泊松方程得到了双栅肖特基势垒MOSFET的解析模型. 这个解析模型包括整个沟道的准二维电势分布和适用于短沟双栅肖特基势垒MOSFET的阈值电压模型.数值模拟器ISE DESSIS验证了模型结果.     

Full-band Monte Carlo investigation of hot carrier trends in thescaling of metal-oxide-semiconductor field-effect transistors

A full-band Monte Carlo (MC) device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) structures. Simulated devices include a conventional MOSFET with a single source/drain implant, a lightly-doped drain (LDD) MOSFET, a silicon-on-insulator (SOI) MOSFET, and a MOSFET built on an epitaxial layer on top of a heavily-doped ground plane. Different scaling techniques have been applied to the devices, to analyze the effects on the electric field and on the energy distributions of the electrons, as well as on drain, substrate, and gate currents. The results provide a physical basis for understanding the overall behavior of impact ionization and gate oxide injection and how they relate to scaling. The observed nonlocality of transport phenomena and the nontrivial relationship between electric fields and transport parameters indicate that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (sub-0.3-μm). In addition, our results suggest that below 0.15 μm, the established device configurations (e.g. LDD) that are successful at suppressing the hot carrier population for longer channel lengths, become less useful and their cost-effectiveness for future circuit applications needs to be reevaluated     

亚微米、深亚微米LDD MOSFET的衬底电流模型中特征长度改进的描述

建立了衬底电流模型中特征长度参数的改进描述,该参数的引入使衬底电流模型能够有效地适用于从微米尺寸到亚微米、深亚微米尺寸的LDD MOSFET.在以双曲正切函数描述的I-V特性基础上,该解析模型的运算量远低于基于数值分析的物理模型,其中提取参数的运用也大大提高了模型的精度,模拟结果与实验数据有很好的一致性.     

亚微米、深亚微米LDD MOSFET的衬底电流模型中特征长度改进的描述

建立了衬底电流模型中特征长度参数的改进描述,该参数的引入使衬底电流模型能够有效地适用于从微米尺寸到亚微米、深亚微米尺寸的L DD MOSFET.在以双曲正切函数描述的I- V特性基础上,该解析模型的运算量远低于基于数值分析的物理模型,其中提取参数的运用也大大提高了模型的精度,模拟结果与实验数据有很好的一致性.     

亚微米、深亚微米LDD MOSFET的衬底电流模型中特征长度改进的描述

建立了衬底电流模型中特征长度参数的改进描述,该参数的引入使衬底电流模型能够有效地适用于从微米尺寸到亚微米、深亚微米尺寸的LDD MOSFET.在以双曲正切函数描述的I-V特性基础上,该解析模型的运算量远低于基于数值分析的物理模型,其中提取参数的运用也大大提高了模型的精度,模拟结果与实验数据有很好的一致性.     

Graded-junction gate/n- overlapped LDD MOSFET structuresfor high hot-carrier reliability

A newly developed gate/n^- overlapped LDD MOSFET was investigated. The MOSFET was fabricated by an oblique rotating ion implantation technique. A formula for the impurity ion profile was derived to analyze the lowering of substrate current and improvement of the degradation caused by the hot-carrier effect of the MOSFET. It was proved that the impurity ion profile near the drain edge is remarkably graded in the directions along channel and toward substrate even just after the implantation, so that the maximum lateral electric field is relaxed as compared with conventional LDD MOSFETs. Also, the maximum point of the lateral electric field at the drain edge is located apart from the main path of the channel current     

Subthreshold behavior models for short-channel junctionless tri-material cylindrical surrounding-gate MOSFET

A novel junctionless tri-material cylindrical surrounding-gate (JLTMCSG) MOSFET is presented in this paper. The subthreshold behavior of JLTMCSG MOSFET is investigated by developing physical based analytical models for channel electrostatic potential, horizontal electric field, and subthreshold current. It is revealed that JLTMCSG MOSFET can effectively suppress DIBL and simultaneously improve carrier transport efficiency. It is also found that subthreshold current for JLTMCSG MOSFET can be significantly reduced by adopting both a small oxide thickness and a thin silicon channel. The accuracy of analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.     

Effect of LDD structure and channel poly-Si thinning on agate-all-around TFT (GAT) for SRAM's

A lightly doped drain (LDD) structure was used in a gate-all-around TFT (GAT). This suppresses the leakage current much more than the LDD used in a single-gate TFT (SGT), and the current level of the GAT with the LDD is almost the same as that of the single-gate TFT (SGT) with the LDD keeping the GAT's advantage of a high on-current. This is because the LDD effectively relaxes the electric field at the drain edge and reduces the effect of the electric field from the surrounded gate of the GAT. Furthermore, the GAT can suppress individual performance variations. The suppression mechanism of the individual performance variation in a GAT was investigated using a poly-Si TFT simulator. The thinner the channel poly-Si, the smaller the individual performance variation of the TFT. The GAT is more effective in decreasing the individual performance variation for thin channels than the SGT because the GAT can achieve the full depletion of the channel poly-Si with a channel thickness twice as large as the SGT. The GAT is eminently suitable for use in high-density, low-voltage operations, and low-power SRAM's     

22nm技术节点异质栅MOSFET的特性研究

研究了22 nm栅长的异质栅MOSFET的特性,利用工艺与器件仿真软件Silvaco,模拟了异质栅MOSFET的阈值电压、亚阈值特性、沟道表面电场及表面势等特性,并与传统的同质栅MOSFET进行比较。分析结果表明,由于异质栅MOSFET的栅极由两种不同功函数的材料组成,因而在两种材料界面附近的表面沟道中增加了一个电场峰值,相应地漏端电场比同质栅MOSFET有所降低,所以在提高沟道载流子输运效率的同时也降低了小尺寸器件的热载流子效应。此外,由于该器件靠近源极的区域对于漏压的变化具有屏蔽作用,从而有效抑制了小尺寸器件的沟道长度调制效应,但是由于其亚阈值特性与同质栅MOSFET相比较差,导致漏致势垒降低效应(DIBL)没有明显改善。     

Suppression of short channel effects by full inversion in deep sub-micron gate SOI MOSFETs

Classical modeling of fully inverted SOI MOSFET (FI MOSFET) has been performed. In FI MOSFETs, the top Si layer is thinner than the thickness of the inversion layer at the conducting state and so the depleted region in the top Si layer is completely eliminated. It was found that the gate electric field induces carriers in the channel more effectively in FI MOSFET than in the fully depleted SOI MOSFETs (FD MOSFET), so that the short channel effects can be suppressed significantly.