基于累加器的内建自测方法研究与分析

在适于采用内建自测方法进行可测性设计的电路中，累加器往往是一种被普遍采用的基本单元，如通用处理器和数字信号处理电路中的算术及逻辑运算电路。文章以Booth乘法器为例，介绍了利用累加器电路进行内建自测输出响应分析的几种常见形式，同时给出了相应的故障覆盖率、硬件开销和时延等方面的比较结果。     

基于可配置LFSR的低功耗确定性矢量生成技术的研究

针对组合电路内建自测试过程中的功耗和故障覆盖率等问题,提出了一种能获得较高故障覆盖率的低功耗测试矢量生成方案。该方案先借助A talanta测试矢量生成工具,针对不同的被测电路生成故障覆盖率较高的测试矢量,再利用插入单跳变测试矢量的方法以及可配置线性反馈移位寄存器生成确定性测试向量的原理,获得低功耗测试矢量。通过对组合电路集ISCAS’85的实验,证实了这种测试生成方案的有效性。     

VLSI流水化格型数字滤波器的内建自测试

格型数字滤波器在信号处理领域得到了广泛应用,本文针对VLSI实现的流水化格型数字滤波器,提出了一种内建自测试方案,不需要对其内部基本功能单元作任何更改,且能在较短时间内检测所有的单固定型故障.所有测试序列都采用简单的算术运算产生.通过对已有功能模块如累加器的复用,作为测试序列生成和响应压缩,该方案能实现真速测试并最大程度的减少了硬件占用和系统性能占用.     

麦克风阵列时延估计的Cramér-Rao界限

 麦克风阵列拓扑结构对麦克风阵列语音处理系统具有重要影响.该文针对麦克风阵列语音处理系统的时延估计性能,通过对声源和麦克风空间位置的几何描述,推导出了时延估计的Cramér-Rao界限,分析了麦克风阵列拓扑结构对其时延估计性能的影响,并给出了常见的麦克风阵列拓扑结构时延估计性能的仿真实验.实验结果有效地验证了理论分析所得出的结论.     

多攻击线引起的串扰时延故障的TPG

探讨了一种串扰时延最大化算法,并且利用被修改的FAN算法,生成测试矢量.对于一条敏化通路,利用被修改的FAN算法适当地激活相应的攻击线和受害线,使电路在最恶劣情况下引起最大通路时延,从而实现更有效的时延测试.利用了FAN算法的多路回退和回溯等主要特色,提高了测试生成算法的效率.实验结果表明,沿着任何临界通路传播的受害线相耦合的攻击线被适当地激活,并且可以对一定规模的电路的串扰时延故障进行测试矢量生成.     

基于扫描链结构重组的低功耗BIST方案

设计了一种改进扫描链结构的内建自测试(BIST)方案.该方案将设计测试序列发生器(TPG)中合适的n状态平滑器与扫描链的重新排序结合起来,从而达到低功耗测试且不致丢失故障覆盖率的目的.通过对15位随机序列信号的测试,发现此TPG中的n状态平滑器在降低功耗的同时还减小了故障覆盖率,遂又设计了重组扫描链的结构来解决这一问题.实验结果表明,该设计方案对于降低平均测试功耗和提高故障覆盖率都具有显著的效果.     

考虑串扰影响的时延测试

超深亚微米工艺下，串扰的出现会导致在电路设计验证、测试阶段出现严重的问题。本文介绍了一个基于波形敏化的串扰时延故障测试生成算法。该算法以临界通路上的串扰时延故障为目标故障进行测试产生．大大提高了算法的效率。实验表明，以该算法实现的系统可以在一个可接受的时间内。对一定规模的电路的串扰时延故障进行测试产生。     

基于时延的软件定义网络快速响应控制器部署

目前大多数针对软件定义网络(SDN)中控制器的部署方案均重点考虑传输时延(PD)对性能的影响,忽略了发送时延(TD)对于部署效果的影响。该文提出基于时延的网络快速响应控制器部署方案。首先,在合理考虑传输和发送两类时延的基础上,完善了已有的平均时延/最大时延最小化模型,并对两种模型是否存在最优解进行了理论证明;其次,利用模糊集理论得出了一种时延优化模型;第三,结合是否考虑发送时延提出了两种部署算法:传输算法和输送算法。为了测试方案的性能,选取实际网络拓扑及数据进行验证。结果表明输送算法在网络的响应速度及稳定性方面优于传输算法,时延优化模型在总时延方面较平均时延/最大时延最小化模型效果更优。     

麦克风阵列时延估计的Cramé-Rao界限

麦克风阵列拓扑结构对麦克风阵列语音处理系统具有重要影响。该文针对麦克风阵列语音处理系统的时延估计性能,通过对声源和麦克风空间位置的几何描述,推导出了时延估计的Cramé-Rao界限,分析了麦克风阵列拓扑结构对其时延估计性能的影响,并给出了常见的麦克风阵列拓扑结构时延估计性能的仿真实验。实验结果有效地验证了理论分析所得出的结论。     

基于动态覆盖率提高门槛值的种子计算方法

为了向可重复播种的LFSR结构提供种子,提出一种基于动态覆盖率提高门槛值(Dynamic Coverage Im-provement Threshold,DCIT)的种子计算方法.使用该方法计算得到的种子进行重复播种,能够截断对提高故障覆盖率效率低的测试码序列.每个种子可以得到长度固定的伪随机测试序列.以ISCAS85基准电路实验结果表明,该方案能够在不降低故障覆盖率的前提下,减少测试矢量长度、缩短测试时间和降低测试功耗.     

A BIST TPG for Low Power Dissipation and High Fault Coverage

This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS'89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS'89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.     

Cell delay fault testing for iterative logic arrays

C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only if an input transition can not be propagated to the cell's output through a path in the cell in a specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all the paths in a cell is first derived, and then necessary conditions for sending this test set to each cell in the array and simultaneously propagating the fault effects to the primary outputs are given. Test set minimization can be solved in a similar way as for the fault cover problem. We use the pipelined array multiplier as an example, and show that it is C-testable with 214 two-pattern tests. With a small number of additional patterns, all the combinational faults can be detected pseudoexhaustive.     

Circular BIST with state skipping

Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion. However, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This "state skipping" logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern-resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added on system paths. Results indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity. Results are also shown for combining "state skipping" logic with observation point insertion to further reduce hardware overhead.     

An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation

This paper presents a novel seed-based test pattern generator (SB-TPG). The core of SB-TPG is a seed sequence generator. A coverage-driven seed generation algorithm has been proposed to generate the optimized seeds. The test sequence generated by SB-TPG is a single input change (SIC) sequence that can significantly reduce test power for test-per-clock built-in self-test (BIST). Further, seed-masking technique has been put forward to filter those power-consuming seeds, thus reducing test power for test-per-scan BIST. Experimental results show that SB-TPG can achieve high fault coverage with short test length, low power and small hardware overhead.     

A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis

This paper presents a partitioned and embedded BIST technique for data path like circuits. The BIST scheme is defined at behavioral level for full optimization of both system and BIST modes during High Level Synthesis. Test time, area overhead and fault coverage are under the scope of the method. User-given constraints on fault coverage to achieve on data path operators and on test time are used to guide the BIST insertion technique towards the lowest area overhead solution.     

Test Cycle Count Reduction in a Parallel Scan BIST Environment

This paper describes a novel method that can be used to reduce test cycle count in a parallel access scan based Built-In-Self-Test (BIST) environment. An algorithm that allows the efficient application of deterministically generated patterns is proposed. This approach allows BIST fault coverage to be increased using deterministic vectors, while minimizing the cost, in terms of test cycles, of applying the vectors.     

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.     

Hardware Generation of Random Single Input Change Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost.It has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. It has also been shown that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non robust tests are under consideration; the experimental results were based on a software generation of RSIC sequences that are easily generated.Obviously, a hardware RSIC generation providing similar results can be obtained. However, this hardware generator must be carefully designed. In this paper, it is explained what are the criteria which must be satisfied for this purpose. A solution is proposed and illustrated with an example. Then, it is shown that a bad result may be obtained if one of these criteria is not satisfied.     

Delay Fault Coverage Enhancement Using Variable Observation Times

Detection of system timing failures has become a very importantproblem whenever high speed system operation is required. It has beendemonstrated that delay fault coverage loss could be significant if improperpropagation paths are used. This occurs when the delay test pair of a targetpropagation path cannot be effectively generated by an ATPG tool, or whenstuck-at test patterns are used as transition (or gate) delay test patterns.In this work, an efficient method is proposed to reduce the amount of faultcoverage loss by using variable observation times. The basic idea is tooffset the shorter propagation paths (really used) by tightening theobservation times. Given a probability distribution of defect sizes and aset of slack differences, this method is able to locate several observationtimes that result in small fault coverage loss.     

一种片上网络路由测试方法研究

对片上网络路由器的结构进行了分析,建立了相应的故障模型.针对此故障模型结合内建自测试,提出了一种基于量子遗传算法的测试矢量传递路径寻优方法.该算法具有收敛速度快,精度高等优点.最后通过对测试故障覆盖率和测试时间进行分析表明这种测试方法具有较高的故障覆盖率、较少的测试时间.