A novel subthreshold slope technique for the extraction of theburied-oxide interface trap density in the fully depleted SOIMOSFET

A novel experimental technique, based on the double-gate operation, is proposed for extracting the back interface trap density of the fully depleted SOI MOSFET. The method relies on simple current-voltage measurements, requires no prior knowledge of the silicon film thickness, and successfully eliminates inaccuracies arising from thickness variations of the accumulation layer, by maintaining both interfaces in depletion. The sensitivity of the technique is shown to depend on the ratio of the interface trap and oxide capacitances of the buried oxide, and is thus limited only by the buried oxide thickness. The technique has been successfully used to monitor the increase in back interface trap density following Fowler-Nordheim stress     

Study of the linear kink effect in PD SOI nMOSFETs

We present in this work a study of the linear kink effect (LKE) occurrence in partially depleted (PD) SOI nMOSFETs with thin gate oxide. The experimental LKE dependence on the channel length, channel width and drain voltage are reported as well as the impact of various parameters on the second peak has been studied by two-dimensional numerical simulations, namely, the gate current level, the carrier lifetime, the increase of the body potential, the threshold voltage variation and AC analysis. Three-dimensional simulations were also performed in order to evaluate the LKE dependence on the channel width.     

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a “C” shape of the threshold voltage corresponding with the second peak in the gm curve.     

Analysis of the subthreshold slope and the linear transconductancetechniques for the extraction of the capacitance coupling coefficientsof floating-gate devices

A critical investigation of the relationship between the floating gate and the accessible terminal voltages reveals that the gate coupling coefficient is overestimated by the traditional expressions obtained from the approximate analysis of the subthreshold slope and the linear transconductance techniques. The investigation further indicates that the subthreshold slope technique is preferred, because the corrections can be easily estimated using the results of auxiliary measurements involving the source and drain coupling coefficients     

Substrate bias and operating temperature effects on the performance of Schottky-barrier SOI nMOSFETs

The substrate bias and operating temperature effects on the performance of erbium-silicided Schottky-barrier SOI nMOSFETs have been studied. The temperature dependence of the threshold voltage, the current ratio of I_ON/I_MIN, and the subthreshold swing has been investigated. From temperature dependence of the drain current, it is confirmed that the carrier transport mechanism changes from thermionic emission and tunneling at low gate voltage to drift-diffusion at the high gate voltage. By applying substrate bias voltage, the I_ON/I_MIN ratio and subthreshold swing can be improved. By investigating the substrate bias dependence of I_ON/I_MIN ratio, subthreshold swing, and DIBL, the optimum substrate bias voltage is suggested.     

Determination of interface and bulk traps in the subthreshold region of polycrystalline silicon thin-film transistors

A simple method to determine the Interface and bulk density of states in polycrystalline silicon thin-film transistors is presented. The energy distribution of the interface trap density has been extracted from analysis of the transfer characteristics in the subthreshold region of operation. Using the obtained interface state distribution, the energy distribution of the bulk traps has been determined by fitting the surface potential at each gate voltage with an analytical theoretical model. Both interface and bulk traps were found to consist of deep states with constant density near the mid-gap and band-tails with density increasing exponentially with the energy when the trap energy approaches the conduction band-edge.     

Effect of doping concentration on the grain boundary trap density and threshold voltage of polycrystalline SOI MOSFETs

PolySOI MOSFETs have been fabricated on undoped and doped polycrystalline silicon films and characterized to study the effect of doping on grain boundary passivation. The grain boundary trap density (N_ST) and threshold voltages have been extracted experimentally to evaluate the extent of grain boundary passivation by the dopants. Charge sheet model based on the effective doping concentration has been employed to analytically estimate the threshold voltages using the experimentally determined grain boundary trap density and grain size (L_g) as model parameters. The variation of threshold voltages with increasing doping concentration for the range of N_A ? (N_ST/L_g) has been studied both by simulation and experiments and the results are presented. Analytically estimated threshold voltages and experimental results show that the threshold voltage falls with increase in the dopant concentration and that this effect is indeed due to the reduction in N_ST as a result of the grain boundary passivation by the dopants.     

Effect of oxide resistance on the characterization of interface trap density in MOS structures

The oxide resistance in a practical MOS capacitor is generally not high enough to be negligible in the evaluation of interface trap density based on the qruasi-static capacitance-voltage (C–V) curve. The importance of the effects of oxide resistance ranging from 10¹³ to 10¹⁶ Ω on the C–V curve and the corresponding interface trap density is theoretically shown. To obtain the oxide resistance in MOS structures the newly reported charge-then-decay method is suggested. From the oxide resistance found, one can compare the distribution curves of interface trap density before and after removing the oxide resistance effect. It is found that the results obtained after removing the oxide resistance effect are more consistent than those without removing it. It addition, the removal of the oxide resistance effect for a sample having a hysteresis C–V behavior is also discussed.     

Analysis of the dependence of the subthreshold swing and the threshold voltage on the substrate voltage of thin-film SOI MOSFETs. Extraction of the interface state densities

A detailed analysis for the variation of the subthreshold swing and the threshold voltage with the substrate voltage of thin film SOI MOSFETs is presented. An accurate model for the subthreshold swing, which emphasizes the optimum back surface regime and applied substrate voltage necessary to obtain the minimum swing, is developed. On the other hand, the modelling of the dependence of the threshold voltage on the substrate voltage is used in combination with the model of the swing in order to extract the interface state densities at both interfaces of the thin Si film.     

Modeling the effect of back gate bias on the subthreshold behavior of a SiGe-channel SOI PMOS device

This paper reports on a simulation study on the back gate bias effect on the subthreshold behavior of a SiGe-channel SOI PMOS device using a device simulator. With a SiGe channel, the SOI PMOS device shows a smaller back gate bias effect as compared to the one without it.     

The effect of nitrogen plasma anneals on interface trap density and channel mobility for 4H-SiC MOS devices

We report results on the introduction of nitrogen at the SiC/SiO₂ interface using a plasma process, thus avoiding the detrimental effects of additional oxidation that accompany other standard nitridation processes, such as annealing in NO gas. The plasma process results in an ‘NO-like’ mobility for approximately 1/6 the interfacial nitrogen content injected via the gas anneal. Direct exposure of the oxide to the plasma is also shown to have a deleterious effect on the breakdown characteristics of the oxide.     

接触面陷阱密度对a-InSnZnO薄膜晶体管器件电气性能的影响研究

We reported the influence of interface trap density（Nt） on the electrical properties of amorphous InSnZnO based thin-film transistors,which were fabricated at different direct-current（DC） magnetron sputtering powers.The device with the smallest N_t of 5.68×10¹¹ cm^-2 and low resistivity of 1.21×10^-3Ω·cm exhibited a turn-on voltage(V_ON) of-3.60 V,a sub-threshold swing（S.S） of 0.16 V/dec and an on-off ratio(I_ON/I_OFF) of⁸ x 108.With increasing N_t,the V_ON,S.S and I_ON/I_OFF were suppressed to-9.40 V,0.24 V/dec and 2.59×10⁸,respectively.The V_TH shift under negative gate bias stress has also been estimated to investigate the electrical stability of the devices.The result showed that the reduction in N_t contributes to an improvement in the electrical properties and stability.     

Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures

The effect of interface state trap density, D_it, on the current-voltage characteristics of four recently proposed III-V MOSFET architectures: a surface channel device, a flat-band implant-free HEMT-like device with δ-doping below the channel, a buried channel design with δ-doping, and implant-free quantum-well HEMT-like structure with no δ-doping, has been investigated using TCAD simulation tools. We have developed a methodology to include arbitrary energy distributions of interface states into the input simulation decks and analysed their impact on subthreshold characteristics and drive current. The distributions of interface states having high density tails that extend to the conduction band can significantly impact the subthreshold performance in both the surface channel design and the implant-free quantum-well HEMT-like structure with no δ-doping. Furthermore, the same distributions have little or no impact on the performance of both flat-band implant-free and buried channel architectures which operate around the midgap.     

Impacts of a buffer layer and hydrogen-annealed wafers on the performance of strained-channel nMOSFETs with SiN-capping layer

In this study, the effects of Si₃N₄ layer capping and TEOS buffer layer inserted prior to the Si₃N₄ deposition on the NMOS device characteristics as well as correlated hot-electron degradations were investigated. The devices were built on two kinds of the substrates, namely, Cz and hydrogen-annealed (Hi) wafers. More importantly, we found that hydrogen species is the primary culprit for aggravated reliabilities in strained devices. By exerting the accelerated stress test, we could study the hot-electron degradation thoroughly in terms of threshold voltage shift (ΔV_TH), transconductance degradation (ΔGm) and so on. The TEOS buffer layer could effectively block the diffusion of hydrogen species from the Si₃N₄ capping layer into the channel and the Si/SiO₂ interface during the Si₃N₄ deposition as well as subsequent thermal cycles.     

Back-gate bias effect on the subthreshold behavior and theswitching performance in an ultrathin SOI CMOS inverter operating at 77and 300 K

The effect of back-gate bias on the subthreshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 300 and 77 K is investigated using a low-temperature device simulator. The simulation results show that the nonzero back-gate bias induces hole pile-up at the back interface, which causes opposite effects on the NMOS and PMOS subthreshold characteristics at 300 and 77 K. Throughout the transient process, at 300 K, for V_B=-5 V operation, hole pile-up at the back interface always exists in the NMOS device. Compared to the zero back-gate bias case, at V_B=-5 V, the risetime of the SOI CMOS inverter is over 5% shorter at 77 and 300 K and the falltime is 5% longer. Prepinch-off velocity saturation in the NMOS device dominates the pull-down transient as a result of the smaller electron critical electric field     

Low-frequency noise in TaSiN/HfO/sub 2/ nMOSFETs and the effect of stress-relieved preoxide interfacial layer

Low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO/sub 2/ on thermal SiO/sub 2/ with stress-relieved preoxide (SRPO) pretreatment. For comparison, control devices were also included with chemical SiO/sub 2/ resulting from standard Radio Corporation of America clean process. The normalized noise spectral density values for these devices are found to be lower when compared to reference poly Si gate stack with similar HfO/sub 2/ dielectric. Consequently, a lower oxide trap density of /spl sim/4/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ is extracted compared to over 3/spl times/10/sup 18/ cm/sup -3/eV/sup -1/ values reported for poly Si devices indicating an improvement in the high-/spl kappa/ and interfacial layer quality. In fact, this represents the lowest trap density values reported to date on HfO/sub 2/ MOSFETs. The peak electron mobility measured on the SRPO devices is over 330 cm/sup 2//V/spl middot/s, much higher than those for equivalent poly Si or metal gate stacks. In addition, the devices with SRPO SiO/sub 2/ are found to exhibit at least /spl sim/10% higher effective mobility than RCA devices, notwithstanding the differences in the high-/spl kappa/ and interfacial layer thicknesses. The lower Coulomb scattering coefficient obtained from the noise data for the SRPO devices imply that channel carriers are better screened due to the presence of SRPO SiO/sub 2/, which, in part, contributes to the mobility improvement.     

Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements

High field electrical stress effects on the mid-gap interface trap density (D_it0) and geometric mean capture cross sections (σ₀) in n-MOSFETs have been studied using the pulsed interface probing method. The results show that the PIP technique is sensitive to changes in mid-gap trap cross section values caused by the Fowler–Nordheim (F–N) electrical stress. The decrease of mid-gap trap cross sections following the F–N tunneling injection is found. Our works also provide further insight into the influence of electrical stress on mid-gap interface trap generation in n-MOSFETs without the assumption of the constant capture cross section value during F–N stresses.     

Effects of Fowler-Nordheim stress on interface trap density andemission cross sections in n-MOSFETs studied by three-level chargepumping

High field Fowler-Nordheim (F-N) stress effects on interface-trap density and emission cross sections in n-MOSFETs have been studied using three-level charge pumping (3LCP). The results show that 3LCP is sensitive to changes in trap cross section as a function of energy in the bandgap. An asymmetric change in electron and hole emission cross sections following F-N tunneling injection is found. The work also provides further insight into the influence of hot electrons on interface trap generation in MOSFETs in both the upper and lower bandgap following electrical stress