3D Electrostatics of Carbon Nanotube Field-Effect Transistors

The three dimensional (3D) electrostatics of carbon nanotube field-effect transistors (CNTFETs) is studied by solving the Poisson equation self consistently with equilibrium carrier statistics of CNTFETs. The 3D Poisson equation is solved using the method of moments. We examine how the 3D environment affects the electrostatics of a 30 nm intrinsic CNT under equilibrium conditions. We show that for a CNTFET with a planar gate, the scaling length (the distance by which the source and drain fields penetrate into the channel) is mostly determined by the gate oxide thickness. The contact geometry can also play an important role on the scaling length. A smaller contact results in shorter scaling length and better gate control. We finally show that the top gated geometry offers obvious advantage over the bottom gated geometry in terms of gate electrostatic control.     

Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance

The gate-all-around (GAA) CNTFET is one of the most efficient types of CNTFETs which provides the conditions for scaling the technology to 10 nm and beyond, due to the extraordinary features of carbon nanotubes and the superior gate control through a high-k insulator over the CNT channel. However, the high CNT-metal contact resistance at the source/drain terminals can significantly degrade the device and circuit performance in CNTFET technology compared to what we have expected. In this study, first a comprehensive comparative assessment of performance and robustness of the gate-all-around CNTFET- and FinFET-based devices and circuits is performed. In the GAA CNTFET-based circuits the contact resistance can be defined as a series resistor at each contacted node of transistors. In addition, an effective circuit-level solution for improving the performance of GAA CNTFET-based circuits in the presence of contact resistance is proposed. In this approach, the contact lengths of the devices located on the critical path are increased to an effective value to reduce the contact resistance considerably and the other contact lengths remain minimum-sized. The results demonstrate that applying this solution significantly improves the speed, energy consumption and energy-delay product of GAA CNTFET-based circuits.     

Electrical characterization and parameter extraction of organic thin film transistors using two dimensional numerical simulations

In this paper a performance based comparison of top and bottom contact organic thin film transistor (OTFT) device structures, using two dimensional numerical simulations has been carried out. In addition to this, investigations pertaining to the estimation of contact resistance in these OTFTs were also performed. To estimate contact resistance the conventional transmission line method and modified transmission line method (M-TLM) were respectively invoked. Our simulation results clearly indicate that the latter is more accurate in the estimation of contact resistance compared to the conventional method. Furthermore, the M-TLM was used to estimate the gate voltage and film thickness dependence of the contact resistance for the two device structures. The observed results have been explained on the basis of the significantly lowered area of carrier injection and extraction regions, at the source/channel and channel/drain interface respectively, in bottom contact transistor that lead to its inferior performance over the top contact transistor.     

NMOSFET ESD self-protection strategy and underlying failuremechanism in advanced 0.13-μm CMOS technology

In this paper, the high current characteristics encountered during electrostatic discharge (ESD) stress using nMOS/L_npn protection devices in a 0.13-μm CMOS technology are investigated for different device parameters: channel length, channel width, gate-oxide thickness, and drain/source contact to gate (DCG/SCG) spacing. From leakage current measurements following ESD stress, it is concluded that the shorter (0.13 μm) devices fail because of source/drain filamentation, whereas longer (0.3 μm) devices with thin (22 Å) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on I_t2. Hot carrier stress experiments additionally revealed that ESD stress can and does affect subsequent hot carrier degradation of the device     

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate–gate charge coupling is investigated at pillar thicknesses in the range of 200–10 nm. For pillar thickness >120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses <60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60–120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behavior are characterized as a function of pillar thickness, and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate–gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation, whereas for pillar thicknesses <60 nm, the increase in the drain current is found to be governed by the inherent gate–gate charge coupling.     

Performance optimization of MOS-like carbon nanotube-FETs based on electrostatic doping

Due to carriers Band-To-Band-Tunneling (BTBT) through channel-source/drain contacts, Conventional MOS-like Carbon Nanotube Field Effect Transistors (C-CNFETs) suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device structure based on electrostatic doping is proposed. The Non-Equilibrium Green’s Function (NEGF) formalism based simulation results show that, with proper choice of tuning voltage, such electrostatic doping strategy can not only reduce the ambipolar conductance but also improve the sub-threshold performance, which are both quite desirable in circuit design to reduce the system power and improve the frequency as well. Further study reveals that the performance of the proposed design depends highly on the choice of tuning voltage value, which should be paid with much attention to obtain a proper trade-off between power and speed in application.     

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.     

Monte Carlo simulation of nanoelectronic devices

The Monte Carlo simulation method is used to analyze the behavior of electron and hole mobility in different nanoelectronic devices including double gate transistors and FinFETs. The impact of technological parameters on carrier mobility is broadly discussed, and its behavior physically explained. Our main goal is to show how mobility in multiple gate devices compares to that in single gate devices and to study different approaches to improve the performance of these devices. Simulations of ultrashort channel devices taking into account quantum effects are also shown.     

Physically based 2D compact model for power bipolar devices

The two‐dimensional (2D) physical compact model for advanced power bipolar devices such as injection enhanced gate transistor (IEGT) or Trench IGBT is presented in this paper. In order to model the complex 2D nature of these devices the ambipolar diffusion equation has been solved simultaneously for different boundary conditions associated with different areas of the device. The IEGT compact model has been incorporated into the SABER simulator and tested in standard double‐pulse switching test circuit. The compact model has been established to model a 4500V‐1500A flat pack TOSHIBA IEGT. Copyright © 2004 John Wiley & Sons, Ltd.     

Temperature-dependent short-channel parameters of FinFETs

The remarkable development and continual proliferation of research in the nanotechnology field have led to improvement in the efficiency of elementary devices. To improve their performance, the parameters of such devices can be scaled down while optimizing their characteristics. However, this simultaneously results in degraded switching characteristics and the appearance of short-channel effects. Multigate-based fin-shaped field-effect transistors (FinFETs) represent a new option to address all these problems. However, thermal failure of FinFET devices under nominal operating conditions is an important issue in the design and implementation of high-speed semiconductor devices. It is also seen that bulk FinFETs exhibit better thermal performance compared with silicon-on-insulator FinFETs. In the work presented herein, various FinFET characteristics including the subthreshold swing, drain-induced barrier lowering, threshold voltage, and drain current were investigated as functions of temperature. The (effective) channel length is larger than the physical gate length (in off-state) due to the undoped underlap regions. This paper also discusses the effects of drain, source, and gate overlap.     

Quantum Simulation Study of a New Carbon Nanotube Field-Effect Transistor With Electrically Induced Source/Drain Extension

In this paper, we present the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism. In this novel CNTFET structure, three adjacent metal cylindrical gates are used, where two side metal gates with lower workfunction than the main gate as an extension of the source/drain on either side of the main metal gate are biased, independent of the main gate, to create virtual extensions to the source and the drain and also to provide an effective electrical screen for the channel region from the drain voltage variations. We demonstrate that the proposed structure of CNTFET shows improvement in device performance focusing on leakage current, on–off current ratio, and voltage gain. In addition, the investigation of short-channel effects for the proposed structure shows improved drain-induced barrier lowering, hot-carrier effect, and subthreshold swing, all of which can affect the reliability of CMOS devices.      

Hot carrier degradation of HfSiON gate dielectrics with TiN electrode

Hot carrier reliability of the HfSiON dielectric with the TiN metal gate electrode has been studied in the nMOS and pMOS short channel transistors. Hot carrier induced degradation of the high-/spl kappa/ gate stack devices are severe than the one in the SiO/sub 2//poly devices. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier contribution induces permanent damage while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress.     

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better V/sub th/-L roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain (g/sub m/R/sub o/) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.     

Simulation of slow current transients and current compression in AlGaAs/GaAs HFETs

Two-dimensional transient simulations of AlGaAs/GaAs HFETs are performed in which substrate traps and surface states are considered. When the drain voltage is raised abruptly, the drain current overshoots the steady-state value, and when it is lowered abruptly, the drain current remains at a low value, showing drain-lag behavior. Turn-on characteristics are also calculated when both the gate voltage and the drain voltage are changed abruptly, and quasi-pulsed I-V curves are derived from them. It is shown that the drain lag due to substrate traps could become a cause of so-called current compression of the HFETs. It is also shown that gate lag due to surface states could become a major cause of the current compression.     

Improved device performance in a CNTFET using La$$_{}$$O$$_{3}$$3 high-$$\kappa $$κ dielectrics

The scaling of MOSFETs is an important and effective way for achieving high performance and low power consumption. One of the bottlenecks for scaling is the physical gate oxide thickness. This paper presents and evaluates a new method for scaling carbon nanotube field-effect transistors (CNTFETs) using \(\hbox {La}_{2}\hbox {O}_{3}\) as a new gate dielectric, which has excellent electrical properties. The proposed CNTFET is simulated using HSPICE. Some of the main digital and analog parameters such as current ratio, subthreshold swing (SS), transconductance, and intrinsic gain have been studied. The simulation results show that the proposed CNTFET outperforms present CNTFETs in terms of current ratio, transconductance, and intrinsic gain.     

New nanoscale band-to-band tunneling junctionless GNRFETs: potential high-performance devices for the ultrascaled regime

High-performance sub-10-nm field-effect transistors (FETs) are considered to be a prerequisite for the development of nanoelectronics and modern integrated circuits. Herein, new band-to-band tunneling (BTBT) junctionless (JL) graphene nanoribbon field-effect transistors (GNRFETs) endowed with sub-10-nm gate length are proposed using a quantum transport simulation. The nonequilibrium Green’s function (NEGF) formalism is used in quantum simulations considering the self-consistent electrostatics and the ballistic transport limit. The computational assessment includes the I_DS–V_GS transfer characteristics, the potential and electron density distributions, the current spectrum, the ambipolar behavior, the leakage current, the subthreshold swing, the current ratio, and the scaling capability. It is found that BTBT JL-GNRFETs can provide subthermionic subthreshold swings and moderate current ratios for sub-10-nm gate lengths. Moreover, a new doping profile, based on the use of lateral lightly n-type-doped pockets, is adopted to boost their performance. The numerical results reveal that BTBT JL-GNRFETs with the proposed doping profile can exhibit improved performance in comparison with uniformly doped BTBT JL-GNRFETs. In addition, the role of the length and n-type doping concentration of the pockets in boosting the device performance is also studied and analyzed while considering the scaling capability of such devices, revealing that low doping concentrations and long pocket lengths are useful for performance improvement. The merits of the BTBT JL-GNRFETs based on the proposed nonuniform doping profile, namely sub-10-nm scale, steep subthermionic subthreshold swing, low leakage current, and improved current ratio and ambipolar behavior, make them promising nanodevices for use in modern nanoelectronics and high-performance integrated circuits.

     

Group III–V ternary compound semiconductor materials for unipolar conduction in tunnel field-effect transistors

A distinct materials combination is presented for tunnel field-effect transistors (TFETs): gallium arsenide phosphide (GaAsP) as a wider-bandgap material in the drain and channel regions with indium gallium arsenide (InGaAs) as a narrow-bandgap material for the source region. The introduction of this novel materials combination greatly improves the ON-state current, OFF-state current, ambipolar behavior, threshold voltage, and subthreshold slope compared with other group III–V ternary heterojunction TFETs. In GaAsP–InGaAs TFETs, the ambipolar current remains equal to the OFF-state current. This paper explores the potential of the proposed device for ultralow-power high-performance applications.     

Bipolar Charge Trapping Induced Anomalous Negative Bias-Temperature Instability in HfSiON Gate Dielectric pMOSFETs

Negative bias-temperature (NBT) stress-induced drain current instability in a pMOSFET with a gate stack is investigated by using a fast transient measurement technique. We find that in certain stress conditions, the NBT-induced current instability evolves from enhancement mode to degradation mode, giving rise to an anomalous turn-around characteristic with stress time and stress gate voltage. Persistent poststress drain current degradation is found in a pMOSFET, as opposed to drain current recovery in its n-type MOSFET counterpart. A bipolar charge trapping model along with trap generation in a HfSiON gate dielectric is proposed to account for the observed phenomena. Poststress single charge emissions from trap states in HfSiON are characterized. Charge pumping and carrier separation measurements are performed to support our model. The impact of NBT stress voltage, temperature, and time on drain current instability mode is evaluated.     

Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

An analytical model was developed to calculate the potential distribution for a gate-underlap double-gate tunnel FET. The electrostatic potential of the device was derived using the two-dimensional Poisson’s equation, incorporating the fringing electric field in the gate-underlap surface and employing a conformal mapping method. In addition to analytical potential modeling, the electric field and drain current were evaluated to investigate the device performance. Excellent agreement with technology computer-aided design (TCAD) simulation results was observed. The dependence of the ambipolar current on the spacer oxide dielectric constant, spacer length, channel length, and gate material thickness was examined using the proposed model. The effects of the variation of all of these parameters were well predicted, and the model reveals that use of a low-\(\kappa \) spacer dielectric combined with a high-\(\kappa \) gate dielectric results in the minimal ambipolar current for the device.     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.