热循环加载条件下SMT焊点应力应变过程的有限元分析

ＳＭＴ焊 热循环条件下的应力应变过程分析是ＳＭＴ焊点可靠性的重要方向。本文采用粘弹塑性材料模式描述ＳｎＰｂ钎料的力学本构响应，对非城堡型ＬＣＣＣ焊蹼结构进行三维有限元分析，考察焊点在热循环加载过程中的应力应变等力学行为。研究结果表明，焊点钎料内的高应力发生在热循环的低温阶段，升降温过程中的蠕变和非弹性应变的累积显著，蠕变应变在非弹性应变中占主导地位，应力应变滞后环在热循环的最初几个周期内就能很快稳     

Reliability screening of high-k dielectrics based on voltage ramp stress

High-k development moves towards integration into CMOS processes rising attention for the reliability assessment. In this paper, the methodology for reliability screening is discussed based on constant voltage stress and voltage ramp stress. It will be shown that both procedures yield equivalent results and the determined reliability parameters are compatible. Better control of the overall measurement time favours the voltage ramp stress as preferred fast screening method for integration of high-k dielectrics.     

Manufacturing issues related to RTP induced overlay errors in aglobal alignment stepper technology

The effect of rapid thermal processing on wafer distortion and overlay accuracy in global alignment photolithography in the fabrication of 0.85 μm CMOS Flash EPROM integrated circuits was studied. Both rapid thermal process parameters and system design (single and multi-lamp processors) were evaluated for their effect on overlay accuracy. It was found that a rapid thermal process (following contact etch and ion implantation) at set temperatures greater than or equal to 950°C resulted in interconnect metallization-to-contact overlay errors in excess of 1.0 μm across the wafer, which led to a 20% functional circuit yield loss. In the case of the single lamp processor, this misalignment was attributed to wafer distortion due to the temperature overshoot during the ramp step, which subsequently resulted in an across wafer temperature range of greater than 120°C. This temperature overshoot and nonuniformity was eliminated by reducing the ramp rate below 100°C/s. This ramp rate reduction, however, decreased the system wafer throughput, and required optimization to eliminate the overlay errors and minimize the effect on throughput. In this study, a 60°C/s ramp rate was found to be optimum. For the multi-lamp RTP system, the metal-to-contact overlay error was not observed. This was believed to be due to the design of the heating mechanism in the multi-lamp processor, which did not produce the large wafer temperature overshoot and nonuniformity that was observed in the single lamp processor     

Analyses of thermal stresses and control schemes for fasttemperature ramps of batch furnaces [IC manufacture]

This work studies fast temperature ramps of batch furnaces under different control schemes based on thermal and stress analyses. A thermal model is first developed to predict temperature distributions on silicon wafers during ramping processes. Thermoelastic model of stresses is then used to predict the onset of slip-line generation under dynamic conditions. Three control schemes, one based on a maximum allowable within-wafer temperature difference, one with a constant cooling rate, and the third based on the condition for onset of slip generation, are then analyzed. The results show that in order to achieve the highest ramp rates while maintaining defect-free wafer processing, the ultimate criterion for temperature control of the furnaces should be the condition for the onset of defect generation instead of the conventional scheme based on constant ramp rates     

Study of unipolar pulsed ramp and combined ramped/constant voltage stress on mos gate oxides

MOS gate oxide capacitors over a wide range of oxide thicknesses (10.9–28 nm) were stressed using a unipolar pulsed voltage ramp and combined ramped/constant voltage stress measurements. The reliability measurements were performed with several different bias conditions in order to assess the effects of the measurement conditions on times to breakdown and breakdown fields. In the first part it was verified that the unipolar pulsed ramp yields breakdown distributions which are identical to those of a widely used staircase ramp. In the second part the unipolar pulsed ramp was used for pre-stress prior to a constant stress and measurement results were compared to those of a ramped/constant stress with a staircase ramp. In several cases a ramp prior to a constant stress increases time to breakdown. The observations made in this study imply that the time to breakdown of a constant stress in the Fowler-Nordheim tunneling regime is strongly dependent on charge trapping and, therefore, on the stressing history of the oxide. Finally, it is shown that the combined ramped/constant voltage stress is a valuable tool for monitoring extrinsic and intrinsic breakdown properties when applying stress parameters in the correct way.     

The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

Characterization on acceleration-factor equation for packaging-solder joint reliability

The well-known Norris-Landzberg acceleration factor (N-L AF) empirical equation was developed based on the accelerated thermal cycling (ATC) test. It has been widely used for many years to predict product lifetimes. However, some recent test results have shown the insufficiency of this equation when the ramp rates change. The AF equation predicts a longer lifetime when the ramp rate is higher, which contradicts the experimental test data. The reason for this discrepancy is that the N-L AF equation combines both ramp rate and dwell time factors in one frequency term. Thus, modifying the current AF equation to more precisely predict product lifetimes has become an important topic.This study proposes a new AF equation to decouple the effects of the ramp rate and dwell time during an ATC test, replacing the frequency term used in the N-L equation with two new terms. One is related to the ramp rate for the strain rate effect, and the other is related to the dwell time for the creep effect of the packaging solder joint material. The new AF equation produces a good correlation between the simulation and test results for different package types discussed in the literature with various ramp rates and dwell times.     

硅/硅直接键合的界面应力

硅/硅直接键合技术广泛应用于SOI,MEMS和电力电子器件等领域,键合应力对键合的成功和器件的性能产生很大的影响。键合过程引入的应力主要是室温下两硅片面贴合时表面的起伏引起的弹性应力;高温退火阶段由于两个硅片的热膨胀系数不同引起的热应力和由于界面的本征氧化层或与二氧化硅键合时二氧化硅发生粘滞流动引起的粘滞应力。另外,键合界面的气泡、微粒和带图形的硅片键合都会引入附加的应力。     

Observation on Defects in Poly-Si Films Prepared by RTCVD Under Nonideal Conditions

Polycrystalline silicon (poly-Si) thin films were deposited on quartz substrates by rapid thermal chemical vapor deposition (RTCVD) under nonideal conditions. Then, crystallographic defects in the poly-Si films were investigated by using transmission electron microscopy (TEM) and optical microscopy combined with defect etching. We found that as-deposited poly-Si films contain a lot of twin crystals, including first-order, second-order, third-order, and higher-order twinned crystals. Besides twinned crystals, stacking faults, dislocations, dislocation nets, dislocation loops, extended dislocations, and dislocation line arrays were also found. Finally, the origins of the defects were analyzed, being attributed to the peculiarities of the RTCVD-quartz growth system, stress caused by lattice and thermal mismatch, a huge temperature ramp, and nonideal deposition conditions. Although our experimental results cannot represent the crystallographic quality of poly-Si films prepared by RTCVD, they at least indicate what kinds and how many defects exist in poly-Si films when deposition conditions severely deviate from the optimum.     

Time-censored ramp tests with stress bound for Weibull lifedistribution

This paper considers ramp tests for Weibull life distribution when there are limitations on test stress and test time. The inverse power law and a cumulative exposure model are assumed. Maximum likelihood estimators of model parameters and their asymptotic covariance matrix are shown. The optimum ramp test plans are given which minimize the asymptotic variance of the ML estimator of a specified quantile of log(life) at design constant stress. The effects of the pre-estimates of design parameters are studied     

Rheology based modeling and design of particle laden polymeric thermal interface materials

Most of the research on particle laden polymeric (PLP) thermal interface materials (TIM) have been primarily focused ob understanding the thermal conductivity of these types of TIMs. For thermal design reduction of the thermal resistance is the end goal. Thermal resistance is not only dependent on the thermal conductivity, but also on the bond line thickness (BLT) of these TIMs. This paper introduces a rheology based model for the prediction of the BLT of these TIMs from very low to very high pressures. BLT depends on the yield stress of the particle laden polymer and the applied pressure. The model is based on the concept of finite size scaling of physical properties of particle laden systems at very thin length scale due to percolation phenomenon in these materials. This paper shows that the yield stress of the PLP increases with decreasing thickness of the TIM and therefore it is size dependent. The BLT model combined with the thermal conductivity model can be used for modeling the thermal resistance of these TIMs for factors such as particle volume faction, substrate/die size, pressure and particle diameter.     

Post-breakdown leakage resistance and its dependence on device area

Sub-nanosecond pulses were used to stress gate capacitors and the post-breakdown leakage resistance is analyzed. Post-breakdown leakage resistance obtained using sub-nanosecond pulse stress and ramp voltage stress are compared, and a power-law relationship between the inverse of the post-breakdown leakage resistance and device area is observed.     

Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.     

a-SiH 热处理过程中纳米硅粒尺寸的控制(英文)

报道了控制热处理过程中含氢非晶硅中纳米硅颗粒大小的一种新方法。用喇曼散射、X射线衍射和计算机模拟,发现在非晶硅中所形成的纳米硅颗粒的大小,随着热退火过程中升温速率的变化而变化。在退火过程中,若非晶硅薄膜升温速率较高(～100℃/s),则所形成纳米硅粒的大小在1.6～15nm;若非晶硅薄膜升温速率较低(～1℃/s),则纳米硅粒大小在23～46nm。根据晶体生长理论,讨论了升温速率的高低与所形成的纳米硅颗粒大小的关系。     

Mechanical strength of 300 mm diameter silicon wafers at high temperatures: modeling and simulation

Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.     

Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits

Finite element modeling (FEM) has been undertaken to characterize the effect of copper (Cu) elasto-plastic behavior on the induction of stress in 3D crystalline silicon (Si) systems incorporating Cu through-silicon vias (TSVs). Using a linear isotropic hardening model, simulations of thermal annealing cycles in Cu TSVs indicate that, for sufficient anneal temperatures, plastic yield within the Cu leads to substantial residual stress in the neighboring Si following cool-down. Simulated Si stress profiles of annealed isolated TSVs agreed with experimental Raman microscopy measurements of post-anneal stress profiles in Si near isolated 5 × 25 μm cylindrical TSVs on a 300 mm Si wafer. Simulations were expanded to investigate the impact of Cu plasticity (yield stress and tangent modulus) on the residual stress profile in Si near isolated TSVs and linear TSV arrays. The results show that the magnitude and extent of the TSV-induced stress field in Si is a non-monotonic function of Cu yield stress. Moreover, the tensile or compressive nature of TSV-induced stress within and outside linear TSV arrays is also a strong function of the Cu yield stress. The simulated impact of Cu tangent modulus on TSV-induced stress in Si is less substantial. The implications of these results for TSV layout with respect to active device placement in a 3D system are discussed.     

Mechanical stress as a function of temperature in aluminum films

Mechanical stress in interconnection is a problem of growing importance in VLSI devices. Open circuits due to metal cracking and voiding and short circuits due to hillocks are stress-related phenomena. The origins of this stress are discussed including intrinsic stresses from the synthesis of the films and thermally induced stresses. A measurement technique based on the determination of wafer curvature with a laser scanning device is utilized to directly measure the film stress in situ as a function of temperature during thermal cycling. The changes in stress observed during thermal cycles are interpreted quantitatively and mechanisms that lead to plastic deformation and their relationship to hillocks are discussed. In the stress vs. temperature measurements, several regions have been identified including elastic and plastic behavior both under compression and tension, the yield strength, recrystallization, gain growth, hardening, and solid-state reactions. The effects of deposition conditions on these regions are also examined     

Analysis of thermal characteristics and mechanism of degradation of flip-chip high power LEDs

The purpose of this study is to investigate the thermal behavior at the die-attached interfaces of flip-chip GaN high-power light emitting diodes (LEDs) using a combination of theoretical and experimental analyses. The results indicate that contact thermal resistance increased dramatically at the die-attached interfaces with aging time and stress, degrading the luminous flux. The junction temperature and thermal uniformity of the flip-chip structure both strongly depend on the arrangement of gold bumps. Local hot spots effectively reduce light output under high electric and thermal stress, influencing the long-term performance of the LED device. The results were validated using finite element analysis and in experiments using an infrared and an emission microscope. A two-step thermal transient degradation mode was identified under various aging stresses. A simulation further optimized the bump configuration that was associated to yield a low junction temperature and high temperature uniformity of the LED chip. Accordingly, the results are helpful in enhancing the performance and reliability of high-power LEDs.     

A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software

This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65-nm random and systematic yield. This infrastructure consists of a 4-Mb addressable-array test circuit with ${> }$8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.      

Optimum simple ramp-tests for the Weibull distribution and type-Icensoring

An optimum simple ramp test-accelerated life test with two different linearly increasing stresses-is presented for the Weibull distribution under type I censoring. It is assumed that the inverse power law holds between the Weibull scale parameter and the constant stress and that the cumulative exposure model for the effect of changing stress applies. The optimum plan-low stress rate and proportion of test units allocated to low stress mode-is found. It minimizes the asymptotic variance of the maximum likelihood estimator of a stated quantile at design stress. For selected values of the design parameters, these optimum plans are tabulated, and the effect of the preestimates of these parameters are studied