A physically-based MOS transistor avalanche breakdown model

A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either infinite multiplication (MI) or finite multiplication with positive feedback of the substrate current (MF) due to the impact ionization in the pinch-off region. The breakdown voltages of these two modes of breakdown have different dependencies on the biasing conditions and device parameters. For MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and can be approximated by the drain saturation voltage plus a constant offset. For MF mode of breakdown, the breakdown voltage decreases as the drain saturation current becomes larger. The calculated breakdown characteristics agree well with the measured ones for devices with effective channel length in the range of 0.44~10 μm     

Study of Transistor Switching Circuit Stability in the Avalanche Region

In the common-emitter transistor switching application, there are occasions in which the collector supply voltage exceeds the transistor sustain voltage. Consequently, the load line could intersect the negative resistance characteristic of the device in the I /sub C/ -V /sub CE/ plane, resulting in a possible unstable or latch-up condition. The purpose of this paper is to study analytically the avalanche region characteristics and their implications for transistor switching applications. The first part is concerned with the derivation of the direct current-voltage relation that, when viewed from the output terminal, represents a negative resistance. The characteristic of this negative resistance depends on the base-emitter circuit condition. The ac terminal behavior is treated in the second part where consideration of the frequency dependence of alpha leads to an equivalent circuit consisting of an inductance in series with a negative resistance. Both elements are nonlinear as well as frequency-dependent. With an external load connected to this nonlinear circuit, a technique of nonlinear analysis is employed to investigate the circuit stability. From this analysis, latch-up and oscillation phenomena in the transistor switching circuit can be predicted. Since the second breakdown involves additional mechanisms besides avalanche multiplication, it is not discussed in this paper.     

Temperature-dependent study of a lattice-matched InP/InGaAlAsheterojunction bipolar transistor

In this work, we report the temperature-dependent characteristics of a new InP/InGaAlAs heterojunction bipolar transistor (HBT). In order to improve the dc performance of conventional InGaAs-based single HBTs, the quaternary In_0.53Ga_0.34Al_0.13As with a wider bandgap is employed as the material for both the base and collector layers. Experimentally, the studied device exhibits a relatively high common-emitter breakdown voltage and low output conductance even at high temperature. Based on the breakdown mechanism of avalanche multiplication, the negative temperature dependence of breakdown voltage is attributed to the positive temperature-dependent impact ionization coefficient. Furthermore, the temperature dependence of current gain is investigated and reported. It is believed that the suppression of hole injection current with decreasing temperature is responsible for the opposite variation of current gains at high current levels     

A Double-Spacer I-MOS Transistor With Shallow Source Junction and Lightly Doped Drain for Reduced Operating Voltage and Enhanced Device Performance

In this letter, a double-spacer (DS) design is utilized for the formation of shallow source and lightly doped drain to further optimize the impact-ionization MOS (I-MOS) transistor structure. The breakdown voltage V_BD needed for avalanche breakdown is lowered due to the shallow source extension. With the formation of the lightly doped drain extension, the impact of drain bias on breakdown voltage, and hence, the threshold voltage V_T is also reduced. The DS I-MOS is fabricated and characterized. Detailed analysis and physical explanation of the impact of drain/gate bias on the device characteristics are provided. Compared to the conventional I-MOS transistor, the shallow source extension reduces the breakdown voltage [drain-induced breakdown voltage lowering (DIBVL)] by 0.3-0.6 V, and the lightly doped drain extension reduces the DIBVL up to 0.17 V/V. In addition, excellent subthreshold swing and good device performance are achieved.     

Temperature dependence of snap-back breakdown up to 300°C analyzed using circuit level model and simulation

The MOS snap-back breakdown and its temperature dependence were investigated up to 300°C using silicided LDD-NMOS transistors. The snap-back sustaining voltage increases from 8.25V at room temperature to 8.9V at 300°C (for L_eff=0.56μm). By using extracted parameters for a simple lumped element model we explain this behaviour originating from an increasing avalanche breakdown voltage and slope of avalanche multiplication factor compensating the increase in bipolar gain with temperature.     

Hot carrier induced bipolar transistor degradation due to basedopant compensation by hydrogen: theory and experiment

New experimental and analytical results are presented which show that extrinsic and intrinsic base dopant compensation by hydrogen is responsible for large changes in the bipolar transistor parameters of emitter-base breakdown voltage (V_ebo), forward collector current (I_c) and series base resistance (R_bx) when such transistors are operated under avalanche and inverted mode stress conditions. A new physical model has been developed to explain the observed changes in V_ebo and I_c as a function of stress time, and the analytical results are shown to be well correlated with the experimental data. Lastly, the effects of degradation on transistor voltage gain bandwidth (f_max) and emitter coupled bipolar comparator delay (τ_delay) are assessed and discussed in terms of circuit performance degradation     

Preparation and properties of Zn delta-doped GaAs/AlGaAs heterojunction phototransistor

We have prepared, characterized and discussed the performance of AlGaAs/GaAs heterojunction bipolar phototransistor (HPT) including Zn delta-doped base. Due to the existence of δ-doped sheets located in the middle of undoped GaAs base the δ-doped HPT devices exhibit low dark current, nearly zero offset voltage, saturation voltage ∼0.4 V, and rise and fall times in ns range at wavelength of 850 nm up to 6 V of applied voltage. Due to avalanche multiplication behavior at the collector junction, an increased optical gain G>10 can be reached for applied voltages in the range of 6-12 V. For voltages higher than the device breakdown voltage (∼12 V) switching and negative differential resistance (NDR) effect is measurable in the inverted mode of operation.     

Avalanche injection and second breakdown in transistors

A rapid type of second breakdown observed in silicon n⁺-p-n-n⁺transistors is shown to be due to avalanche injection at the collector n-n⁺junction. Localized thermal effects, which are usually associated With second breakdown, are shown to play a minor role in the initiation of the transition to the low voltage state. A useful tool in the analysis of avalanche injection is the n⁺-n-n⁺diode, which exhibits negative resistance at a critical voltage and current. A close correspondence between the behavior of the diode and the transistor (open base) is established both theoretically and experimentally. Qualitative agreement with the proposed model is obtained for both directions of base current flow. It is shown that transistors having thin, lightly doped collector regions are particularly susceptible to avalanche injection, which suggests that some compromise may be necessary in the design of high-frequency power transistors.     

Avalanche multiplication and pinch-in models for simulating electrical instability effects in SiGe HBTs

The onset of impact ionization-induced instabilities limits the operative range of SiGe hetero-junction bipolar transistors. Based on referential Monte Carlo simulation results, a critical review of major models for the avalanche multiplication factor (M) is presented, and a new analytical model is proposed and successfully verified by measurements. The novel M formulation has been incorporated in a two-dimensional theoretical model describing bipolar transistor operation under pinch-in conditions/above the open-base breakdown voltage BV_CEO. The physical mechanisms leading to electrical instability are addressed, and closed form analytical relations defining the onset of instability under forced-I_E conditions are derived. The proposed model defines the limits of the Safe Operating Area (SOA) related to impact ionization, enabling the reliable usage of HBTs above BV_CEO.     

The anomalous avalanche breakdown

Normally, the breakdown voltage of a p-n junction decreases with increasing doping density. But there are also cases in which the breakdown voltage increases with increasing doping density, e.g., for InSb in the doping range from 10¹³cm^-3to 2 × 10¹⁴cm^-3. The reason for the anomalous behavior is the saturation of the ionization coefficient with increasing electric field strength. The anomalous behavior can only be observed if the tunnel breakdown requires a higher field strength as the one required for saturation of the ionization coefficient. This paper presents a rather simple theory yielding analytical solutions for the normal and anomalous avalanche breakdown. Treated is the influence of the doping profile upon the breakdown voltage in plane junctions and the influence of the radius of curvature for cylindrical one-sided abrupt junctions. The influence of the temperature upon the breakdown voltage and the multiplication factor as function of voltage is calculated for one-sided abrupt plane junctions. Finally, the temperature and doping range for the anomalous avalanche breakdown and the transition region is plotted for the semiconductors InSb, InAs, CdHgTe, PbSnTe, Ge, Si, GaAs, and GaP.     

RF linearity characteristics of SiGe HBTs

Two-tone intermodulation in ultrahigh vacuum/chemical vapor deposition SiGe heterojunction bipolar transistors (HBTs) were analyzed using a Volterra-series-based approach that completely distinguishes individual nonlinearities. Avalanche multiplication and collector-base (CB) capacitance were shown to be the dominant nonlinearities in a single-stage common emitter amplifier. At a given I_c an optimum V_ce exists for a maximum third-order intercept point (IIP3). The IIP3 is limited by the avalanche multiplication nonlinearity at low I_c, and limited by the C_CB nonlinearity at high I_c. The decrease of the avalanche multiplication rate at high I_c is beneficial to linearity in SiGe HBTs. The IIP3 is sensitive to the biasing condition because of strong dependence of the avalanche multiplication current and CB capacitance on I_c and V_ce. The load dependence of linearity was attributed to the feedback through the CB capacitance and the avalanche multiplication in the CB junction. Implications on the optimization of the transistor biasing condition and transistor structure for improved linearity are also discussed     

雪崩光电探测器的击穿效应模型分析

基于CMOS工艺制备了空穴触发的Si基雪崩探测器(APD),基于不同工作温度下器件的击穿特性,建立空穴触发的雪崩器件的击穿效应模型。根据雪崩击穿模型和击穿电压测试结果,拟合曲线得到击穿电场与温度的关系参数(dE/dT),器件在250～320 K区间内,击穿电压与温度是正温度系数,器件发生雪崩击穿为主,dV/dT=23.3 mV/K,其值是由倍增区宽度以及载流子碰撞电离系数决定的。在50～140 K工作温度下,击穿电压是负温度系数,器件发生隧道击穿,dV/dT=-58.2 mV/K,其值主要受雪崩区电场的空间延伸和峰值电场两方面因素的影响。     

Functional AlGaAs/GaAs heterostructure-emitter bipolar transistor with a pseudomorphic InGaAs/GaAs quantum-well base

A new functional AlGaAs/GaAs heterostructure-emitter bipolar transistor (HEBT) with a pseudomorphic InGaAs/GaAs quantum-well (QW) base structure is presented. Due to the insertion of an InGaAs QW between the emitter–base (E–B) junction, the valence band discontinuity can be enhanced. The excellent transistor characteristics including a high current gain of 280 and a low offset voltage of 100 mV are obtained. In addition, an interesting multiple S-shaped negative differential resistance (NDR) phenomenon is observed under the inverted operation mode. This may be attributed to an avalanche multiplication and sequential two-stage barrier lowering effect.     

用于光子计数的InGaAs/InP SPAD设计

重点研究了InGaAs/InP SPAD的隧道贯穿电场、雪崩击穿电场、雪崩宽度与过偏电压的关系,提出了过偏电压的计算方法.分析了InGaAs/InP SPAD的基本特性即探测效率、暗计数率与其过偏电压、工作温度、量子效率、电场分布的依赖关系,提出了一种单光子InGaAs雪崩二极管的设计方法.设计制作了InGaAs/InP SPAD,并在门控淬灭模式下进行了单光子探测实验.结果表明:对于200m的SPAD,在过偏2 V、温度-40 ℃条件下,探测效率(PDE) 20%(1 550 nm)、暗计数率(DCR)20 kHz;对于50m的SPAD,在过偏2.5 V、温度-40 ℃条件下,探测效率(PDE) 23%(1 550 nm)、暗计数率(DCR)2 kHz.最后对实验结果进行了分析和讨论.     

An 1800 V triple implanted vertical 6H-SiC MOSFET

6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n ⁺ source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 μA/cm² for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm² delivers a forward drain current of 0.3 A at Y_GS=10 V and V _DS=8 V. The specific on resistance was determined to 82 mΩdcm² at 50 mV drain source voltage and at V_GS =10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer     

An analytical avalanche breakdown model for double gate MOSFET

An analytical model of avalanche breakdown for double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is presented. First of all, the effective mobility (μ_eff) model is defined to replace the constant mobility model. The channel length modulation (CLM) effect is modeled by solving the Poisson’s equation. The avalanche multiplication factor (M) is calculated using the length of saturation region (ΔL). It is shown that the avalanche breakdown characteristics calculated from the analytical model agree well with commercially available 2D numerical simulation results. Based on the results, the reliability of the DG MOSFET can be estimated using the proposed analytical model.     

Temperature-dependence investigation of a high-performance inverteddelta-doped V-shaped GaInP/InxGa1-xAs/GaAspseudomorphic high electron mobility transistor

A newly designed inverted delta-doped V-shaped GaInP/In_xGa_1-xAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) has been successfully fabricated and studied. For a 1×100 μm² device, a high gate-to-drain breakdown voltage over 30 V at 300 K is found. In addition, a maximum transconductance of 201 mS/mm with a broad operation regime for 3 V of gate bias (565 mA/mm of drain current density), a very high output drain saturation current density of 826 mA/mm, and a high DC gain ratio of 575 are obtained. Furthermore, good temperature-dependent performances at the operating temperature ranging from 300 to 450 K are found. The unity current gain cutoff frequency f_T and maximum oscillation frequency f_max up to 16 and 34 GHz are obtained, respectively. Meanwhile, the studied device shows the significantly wide and flat gate bias operation regime (3 V) for microwave performances     

10Gbit/s InGaAs/InP雪崩光电二极管

基于InGaAs/InP吸收区、渐变区、电荷区和倍增区分离雪崩光电二极管(SAGCMAPD)器件结构,利用数值计算方法,模拟了各层参数对器件频率响应特性的影响.模拟结果表明,吸收层、倍增层厚度及电荷层面电荷密度可影响器件的-3 dB带宽;随增益的增加,器件带宽会逐渐降低;电荷层面电荷密度对器件击穿电压有明显影响.结合此模拟结果,制作出了高速InGaAs/InP雪崩光电二极管,并对器件进行了封装测试.测试结果表明,该结果与模拟结果相吻合.器件击穿电压为30 V;在倍增因子为1时,器件响应度大于0.8 A/W;在倍增因子为9时,器件暗电流小于10 nA,-3 dB带宽大于10 GHz,其性能满足10 Gbit/s光纤通信应用要求.     

Design and analysis of separate-absorption-transport-charge-multiplication traveling-wave avalanche photodetectors

This paper proposes a novel type of avalanche photodiode-the separate-absorption-transport-charge-multiplication (SATCM) avalanche photodiode (APD). The novel design of photoabsorption and multiplication layers of APDs can avoid the photoabsorption layer breakdown and hole-transport problems, exhibit low operation voltage, and achieve ultra-high-gain bandwidth product performances. To achieve low excess noise and ultra-high-speed performance in the fiber communication regime (1.3/spl sim/1.55 /spl mu/m), the simulated APD is Si-based with an SiGe-Si superlattice (SL) as the photoabsorption layer and traveling-wave geometric structures. The frequency response is simulated by means of a photo-distributed current model, which includes all the bandwidth-limiting factors, such as the dispersion of microwave propagation loss, velocity mismatch, boundary reflection, and multiplication/transport of photogenerated carriers. By properly choosing the thicknesses of the transport and multiplication layers, microwave propagation effects in the traveling-wave structure can be minimized without increasing the operation voltage significantly. A near 30-Gb/s electrical bandwidth and 10/spl times/ avalanche gain can be achieved simultaneously, even with a long device absorption length (150 /spl mu/m) and low operation voltage (/spl sim/12 V). In addition, the ultrahigh output saturation power bandwidth product of this simulated TWAPD structure can also be expected due to the large photoabsorption volume and superior microwave-guiding structure.     

雪崩管最佳倍增因子线性化温控技术研究

为了进一步增强机载激光测距机在全温范围内的环境适应性,分析了温度与探测器模块输出功率信噪比的关系,推导了最佳倍增因子与温度的方程式,阐述了温度变化引起倍增因子对最佳雪崩倍增因子偏离的原因。根据雪崩管探测器雪崩击穿电压的线性温度特性,设计了机载温度范围为-55℃~70℃的基于自然对数法的最佳倍增因子雪崩偏压线性化温控电路,用于补偿因温度变化所引起的倍增因子对最佳雪崩倍增因子的偏离。结果表明,实测雪崩偏压温控系数为2.29V/℃,与理论分析值误差仅为4%。该技术用于新型机载激光测距系统中,获得了良好的试验数据,满足机载环境的特殊需求。