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嵌入式实时操作系统eCos内存分配策略的分析 总被引:3,自引:1,他引:2
本文全面深入的探讨了eCos中内存分配策略的实现。首先,对eCos内核及内存管理方法进行了介绍,然后对四种内存分配策略进行了阐述和性能比较。对于嵌入式系统和应用的开发具有一定的参考价值。 相似文献
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为了解决嵌入式设备中内存频繁分配和释放所引起的内存碎片以及浏览器正常运行难问题,提出具有垃圾回收机制的可动态增长池式分配数据结构设计和具有Compaction机制的Vector分配方法;在嵌入式环境系统设计时,采用可回收动态增长池式分配策略,系统无需预测内存大小,而且可以循环使用池内空间;Compaction机制的Vector分配方法可以移动"在用"对象和"废弃"对象调整内存占用,减少碎片。实验设计中应用上述策略,验证了该内存管理效率比系统级效率要高,嵌入式设备中打开网页文件越大,体现出来的效率更高。 相似文献
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嵌入式操作系统μC/OS-Ⅱ的一种内存管理算法 总被引:1,自引:1,他引:0
针对μc/OS-Ⅱ内存管理机制的不足,提出了一种新的内存管理算法.较小的内存分成固定大小的内存块,用位图索引组织;较大的内存用链表组织.实验表明,该方法能较好地提高内存分配速度和利用率,特别是对于内存块大小变化很大的系统. 相似文献
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Some unsafe languages, like C and C+ + , let programmers maximize performance but are vulnerable to memory errors which can lead to program crashes and unpredictable behavior. Aiming to solve the problem, traditional memory allocating strategy is improved and a new probabilistic memory allocation technology is presented. By combining random memory allocating algorithm and virtual memory, memory errors are avoided in all probability during software executing. By replacing default memory allocator to manage allocation of heap memory, buffer overflows and dangling pointers are prevented. Experiments show it is better than Die-hard of the following aspects: memory errors prevention, performance in memory allocation set and ability of controlling working set. So probabilistic memory allocation is a valid memory errors prevention technology and it can tolerate memory errors and provide probabilistic memory safety effectively. 相似文献
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Bit allocation or the quantizer assignment problem is a basic and essential issue in lossy picture coding. The optimal solution for the bit allocation problem can be found by the Lagrangian method. However, it requires much computational time and memory. To reduce complexity overhead, we propose a fast scheme using a picture activity measure. Comparison among the existing activity measurement methods is presented to select the most reliable activity measure and the mapping relation between the activity value, and a quantization parameter is proposed. 相似文献
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Shouzhen Gu Qingfeng Zhuge Juan Yi Jingtong Hu Edwin H.-M. Sha 《Journal of Signal Processing Systems》2016,84(1):151-162
As the advance of memory technologies, multiple types of memories such as different kinds of non-volatile memory (NVM), SRAM, DRAM, etc. provide a flexible configuration considering performance, energy and cost. For improving the performance of systems with multiple types of memories, data allocation is one of the most important tasks. The previous studies on data allocation problem assume the worst (fixed) case of data-access frequencies. However, the data allocation produced by employing worst case usually leads to an inferior performance for most of time. In this paper, we model this problem by probabilities and design efficient algorithms that can give optimal-cost data allocation with a guaranteed probability. We propose DAGP algorithm produces a set of feasible data allocation solutions which generates the minimum access time or cost guaranteed by a given probability. We also propose a polynomial-time algorithm, MCS algorithm, to solve this problem. The experiments show that our technique can significantly reduce the access cost compared with the technique considering worst case scenario. For example, comparing with the optimal result generated by employing the worst cases, DAGP can reduce memory access cost by 9.92 % on average when guaranteed probability is set to be 0.9. Moreover, for 90 percents of cases, memory access time is reduced by 12.47 % on average. Comparing with greedy algorithm, DAGP and MCS can reduce memory access cost by 78.92 % and 44.69 % on average when guaranteed probability is set to be 0.9. 相似文献
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NAND Flash具有高存储密度和高存储速率的特点,在嵌入式系统领域得到了广泛应用.但其固有的擦除机制和存在有坏块这一致命弱点,成为其在应用中的主要障碍.本文提出了一种应用于FAT文件系统上的坏块处理方法,使用Flash上其他的空闲块或者空闲空间来代替坏块,并将坏块在FAT表中作出标记以后不作使用.这种方法彻底屏蔽了坏块对上层应用的影响,并对存储介质没有造成任何不良影响,从而很好地克服了上述障碍.工程项目中的应用证明了其较高的可靠性. 相似文献
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In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints for embedded applications. Our procedure consists of application of loop transformations and reordering of array accesses to reduce the memory bandwidth followed by memory allocation and assignment procedures based on ILP models and heuristic-based algorithms. The specific problems include determination of (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy consumption is minimum for a given memory configuration (number of modules, size and number of ports per module). The results obtained by the heuristics match well with those obtained by the ILP methods. 相似文献
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Khouri K.S. Lakshminarayana G. Jha N.K. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(5):513-524
This paper presents a memory binding algorithm for behaviors, used in application-specific integrated circuits (ASICs), that are characterized by the presence of conditionals and deeply nested loops that access memory extensively through arrays. Unlike previous works, this algorithm examines the effects of branch probabilities and allocation constraints. First, we demonstrate, through examples, the importance of incorporating branch probabilities and allocation constraint information when searching for a performance-efficient memory binding. We also show the interdependence of these two factors and how varying one without considering the other may greatly affect the performance of the behavior. Second, we introduce a memory binding algorithm that has the ability to examine numerous bindings by employing an efficient performance estimation procedure. The estimation procedure exploits locality of execution, which is an inherent characteristic of target behaviors. This enables the performance estimation technique to look at the global impact of the different bindings, given the allocation constraints. We tested our algorithm using a number of benchmarks from the parallel computing domain. A series of experiments demonstrates the algorithm's ability to produce bindings that optimize performance, meet memory allocation constraints, and adapt to different resource constraints and branch probabilities. One limitation of our algorithm is that, in its current form, it is not well suited for system-on-a-chip synthesis where there is complex communication between general-purpose microprocessors that use custom-designed arrays. Results show that the algorithm requires 41% fewer memories with a performance loss of only 0.2% when compared to a parallel memory architecture. When compared to the best of a series of random memory bindings, the algorithm improves schedule performance by 22%. 相似文献
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Junghoon Kim Taehun Kim Changwoo Min Hyung Kook Jun Soo Hyung Lee Won‐Tae Kim Young Ik Eom 《ETRI Journal》2014,36(5):741-751
Smart TV is expected to bring cloud services based on virtualization technologies to the home environment with hardware and software support. Although most physical resources can be shared among virtual machines (VMs) using a time sharing approach, allocating the proper amount of memory to VMs is still challenging. In this paper, we propose a novel mechanism to dynamically balance the memory allocation among VMs in virtualized Smart TV systems. In contrast to previous studies, where a virtual machine monitor (VMM) is solely responsible for estimating the working set size, our mechanism is symbiotic. Each VM periodically reports its memory usage pattern to the VMM. The VMM then predicts the future memory demand of each VM and rebalances the memory allocation among the VMs when necessary. Experimental results show that our mechanism improves performance by up to 18.28 times and reduces expensive memory swapping by up to 99.73% with negligible overheads (0.05% on average). 相似文献
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Appropriate allocation of decision-making tasks between processing levels in a hierarchical memory network pattern classifier can enhance efficient utilisation of resources and reduce implementation complexity. The letter describes and compares two strategies for such resource allocation, with specific reference to decision refinement between processing levels. 相似文献
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Faidon C. George I. 《AEUE-International Journal of Electronics and Communications》2008,62(5):356-364
We present a technique for dynamic allocation of memory to different queues. Our approach lies between two well-known techniques, linked lists and the relocation of data for preserving reasonable contiguous areas of available memory space. However, we avoid the main drawbacks of both. We never allocate more than two segments of contiguous memory per flow and thus avoid the proliferation of pointers and associated memory fragmentation. Moreover, we never relocate data already admitted into memory. We thus offer a considerably simpler implementation, amenable to hardware realization. The price to pay is also twofold. We cannot guarantee total exhaustion of the available memory before overflow occurs and we can only implement the first in first out (FIFO) discipline for the flows hosted in memory. In fact, we exploit the defining feature of a FIFO: data having arrived first will also leave first, spending in memory as little time as possible and giving the opportunity for rearranging memory allocation to the advantage of future arrivals. Two segments per flow are sufficient to achieve, over time, complete memory reallocation without data movement. Simulation results exhibit this ‘refreshing’ feature of FIFO, as brought to light by our proposed scheme. 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(3):403-416
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一种改进的通用ASN.1协议编解码方法 总被引:1,自引:1,他引:0
针对开源ASN1C采用动态内存分配方法处理ASN.1协议消息的可选参数,导致编解码软件由于频繁分配和释放内存操作而带来的问题提出了一种改进的方法,避免了ASN.1结构类型编解码中的动态内存分配,减少了整个协议编解码软件进行内存分配和释放操作的频度.测试和实际工程运行结果表明,改进的方法提高了编解码软件的可用性、执行效率和健壮性. 相似文献