Dopant diffusion studies and free carrier lifetimes during rapid thermal processing of semiconductors

Rapid thermal processing of semiconductors involves significant photonic and subsequent thermal excitation. In the past, photonic excitation during rapid thermal annealing had been speculated to lead to significant enhancement of dopant diffusion or activation. In this work we present some experimental results indicating the absence of any such enhancement at high temperatures (1000–1050°C) which most often are employed during the metal-oxide–semiconductor device processing. The implanted dopant (boron, arsenic or phosphorus) movement in silicon during different rapid thermal annealing conditions was studied using secondary ion mass spectroscopy (SIMS) technique. To understand the effect of point defects in controlling the diffusion process, the concentrations of charged and neutral point defects were calculated as a function of carrier concentration using previously published defect-carrier relations. The dependence of free carrier concentration on lattice perturbation parameters such as impurities and temperature was formulated and used in calculating carrier lifetimes (τ) in silicon. We qualitatively analyze two competing reactions, (i) the phonon release at the defect sites and (ii) the Auger electron process due to many electron interactions, to explain the apparent absence of any enhanced dopant diffusion. In our analyses, we obtain a highest free carrier lifetime of about 442 ns in the case of low dose (1e13/cm²) implanted sample during the transient stage (700°C) of the dopant activation cycle. The corresponding smallest (17 fs) free carrier lifetime was obtained for the high dose implanted sample (dopants already activated) at 1000°C, the steady state part of an extended anneal cycle. Based on the detailed free carrier lifetime analyses, we suggest that any enhanced dopant activation or diffusion, at the best, may occur only at very low temperatures in the samples implanted with low doses of dopant atoms.     

High temperature transport kinetics in heteroepitaxial LaFeO3 thin films

Heteroepitaxial LaFeO₃(1 1 0) thin films with a thickness of 150 nm were grown on LaAlO₃(0 0 1) by reactive sputtering in an inverted cylindrical magnetron geometry. Equilibrium conductivity was measured as a function of partial pressure of oxygen at T=1000 °C, and logσ plotted vs. logP(O₂) showed a minimum in conductivity for P(O₂)=10⁻¹¹ atm and a linear response between 10⁻¹⁰ and 1 atm. This linear response makes thin films of LaFeO₃ a promising material for oxygen sensor applications. We have also measured the time response of the film conductivity upon an abrupt change in the partial pressure of ambient oxygen from 10⁻² to 10⁻³ atm, which was determined at 60 s for T=700 °C and <3.5 s at T=1000 °C.     

Comparison of p–n junction formed by BF2 and B implantation in silicon microstrip detector with low and high thermal budget: impact of fluorine on electrical characteristics

The influence of crystal damage on the electrical properties and the doping profile of the implanted p⁺–n junction has been studied at different annealing temperatures using process simulator TMA-SUPREM4. This was done by carrying out two different implantations; one with implantation dose of 10¹⁵ BF₂⁺ ions/cm² at an energy of 80 keV and other with 10¹⁵ B⁺ ions/cm² at 17.93 keV. Substrate orientation 1 1 1 of phosphorus-doped n-type Si wafers of resistivity 4 kΩ cm and tilt 7° was used, and isochronally annealing was performed in N₂ ambient for 180 min in temperature range between 400°C and 1350°C. The diode properties were analysed in terms of junction depth, sheet resistance. It has been found that for low thermal budget annealing, boron diffusion depth is insensitive to the variation in annealing temperature for BF₂⁺-implanted devices, whereas, boron diffusion depth increases continuously for B⁺-implanted devices. In BF₂⁺-implanted devices, fluorine diffusion improves the breakdown voltage of the silicon microstrip detector for annealing temperature upto 900°C.For high thermal budget annealing, it has been shown that the electrical characteristics of BF₂⁺-implanted devices is similar to that obtained in B⁺-implanted devices.     

Vibrational spectroscopy characterization of low-dielectric constant SiOC:H films prepared by PECVD technique

Low-dielectric constant SiOC:H films were prepared by plasma enhanced chemical vapour deposition (PECVD) from trimethyl-silane (H–Si–(CH₃)₃) and ozone (O₃) gas mixture. The samples were preliminarily annealed at 400 °C in N₂ atmosphere and then in N₂+He plasma. Afterwards, they were treated in vacuum at some fixed temperatures in the range between 400 and 900 °C. Structural investigations of the annealed films were carried out by means of vibrational spectroscopy techniques. FT-IR spectrum of a preliminarily treated sample shows absorption bands due to stretching modes of structural groups like Si–CH₃ at 1270 cm⁻¹, Si–O–Si at 1034 cm⁻¹ and C–H_x in the region between 2800 and 3000 cm⁻¹. No significant spectral change was observed in the absorption spectra of samples annealed up to 600 °C, indicating that the preliminarily treated film retains a substantial structural stability up to this temperature. Above 600 °C, absorption spectra show a strong quenching of H-related peaks while the band due to Si–O–Si anti-symmetric stretching mode shifts towards higher energy, approaching the value observed for thermally grown SiO₂. Raman spectra of samples treated at temperatures T500 °C exhibit both D and G bands typical of sp²-hybridised carbon, due to the formation of C–C bonds within the film which is accompanying the release of hydrogen. The intensity of D and G bands becomes more pronounced in samples annealed at higher temperatures, thus suggesting a progressive precipitation of carbon within the oxide matrix.     

Correlation between infrared transmission spectra and the interface trap density of SiO2 films

This work is an attempt to estimate the electrical properties of SiO₂ thin films by recording and analyzing their infrared transmission spectra. In order to study a big variety of films having different infrared and electrical properties, we studied SiO₂ films prepared by low pressure chemical vapor deposition (LPCVD) from SiH₄ + O₂ mixtures at 425 °C and annealed at 750 °C and 950 °C for 30 min. In addition thermally grown gate quality SiO₂ films of similar thickness were studied in order to compare their infrared and electrical properties with the LPCVD oxides. It was found that all studied SiO₂ films have two groups of Si–O–Si bridges. The first group corresponds to bridges located in the bulk of the film and far away from the interfaces, the grain boundaries and defects and the second group corresponds to all other bridges located near the interfaces, the grain boundaries and defects. The relative population of the bulk over the boundary bridges was found equal to 0.60 for the LPCVD film after deposition and increased to 4.0 for the LPCVD films after annealing at 950 °C. Thermally grown SiO₂ films at 950 °C were found to have a relative population of Si–O–Si bridges equal to 3.9. The interface trap density of the LPCVD film after deposition was found equal to 5.47 × 10¹² eV⁻¹ cm⁻² and decreases to 6.50 × 10¹⁰ eV⁻¹ cm⁻² after annealing at 950 °C for 30 min. The interface trap density of the thermally grown film was found equal to 1.27 × 10¹¹ eV⁻¹ cm⁻² showing that films with similar Si–O–Si bridge populations calculated from the FTIR analysis have similar interface trap densities.     

Growth and physical properties of in situ phosphorus-doped RTLPCVD polycrystalline silicon thin films

In situ phosphorus-doped (P-doped) polysilicon (poly-Si) thin films are obtained by rapid thermal low pressure chemical vapor deposition (RTLPCVD) in a single chamber RTP machine by using diluted silane (SiH₄/Ar=10%) and phosphine (PH₃=200 ppm). Deposition kinetics of poly-Si films were studied in the 600–850°C temperature range at fixed total pressure of 2 mbar and gas flow rate (100 sccm). Activation energy of 1.82 eV was calculated in the surface reaction deposition regime. Dopant activation has been obtained sequentially by RTO at 1000°C in pure O₂ atmosphere. This later process permits to both activate the phosphorus dopant and forms an ultrathin polyoxide which blocks dopant outdiffusion. Secondary ion-mass spectrometry (SIMS) analysis showed flat P-dopant profiles throughout the film thickness with a P concentration varying from 5.5×10²⁰ to 2.4×10¹⁹ at/cm³ when the deposition temperature increases in the 600–850°C range. Grazing incidence X-ray diffraction (XRD) has been used to study the structural properties of the poly-Si layers. It appeared particularly that the amorphous to crystalline temperature transition occurs at around 650°C. Finally, four-point probe measurements showed that sheet resitivities in the mΩ cm range can be routinely achieved for in situ P-doped RTLPCVD poly-Si films.     

Influence of rapid thermal annealing on morphological and electrical properties of RF sputtered AlN films

Aluminum nitride films were deposited, at 200 °C, on silicon substrates by RF sputtering. Effects of rapid thermal annealing on these films, at temperatures ranging from 400 to 1000 °C, have been studied. Fourier transform infrared spectroscopy (FTIR) revealed that the characteristic absorption band of Al–N, around 684 cm⁻¹, became prominent with increased annealing temperature. X-ray diffraction (XRD) patterns exhibited a better, c-axis, (0 0 2) oriented AlN films at 800 °C. Significant rise in surface roughness, from 2.1 to 3.68 nm, was observed as annealing temperatures increased. Apart from these observations, micro-cracks were observed at 1000 °C. Insulator charge density increased from 2×10¹¹ to 7.7×10¹¹ cm⁻² at higher temperatures, whereas, the interface charge density was found minimum, 3.2×10¹¹ eV⁻¹cm⁻², at 600 °C.     

Investigation of strontium tantalate thin films for high-k gate dielectric applications

Strontium tantalate (STO) films were grown by liquid-delivery (LD) metalorganic chemical vapor deposition (MOCVD) using Sr[Ta(OEt)₅(OC₂H₄OMe)]₂ as precursor. The deposition of the films was investigated in dependence on process conditions, such as substrate temperature, pressure, and concentration of the precursor. The growth rate varied from 4 to 300 nm/h and the highest rates were observed at the higher process temperature, pressure, and concentration of the precursor. The films were annealed at temperatures ranging from 600 to 1000 °C. Transmission electron microscopy (TEM), X-ray diffraction (XRD), and ellipsometry indicated that the as-deposited and the annealed films were uniform and amorphous and a thin (>2 nm) SiO₂ interlayer was found. Crystallization took place at temperatures of about 1000 °C. Annealing at moderate temperatures was found to improve the electrical characteristics despite different film thickness (effective dielectric constant up to 40, the leakage current up to 6×10⁻⁸ A/cm², and lowest midgap density value of 8×10¹⁰ eV⁻¹ cm⁻²) and did not change the uniformity of the STO films, while annealing at higher temperatures (1000 °C) created voids in the film and enhanced the SiO₂ interlayer thickness, which made the electrical properties worse. Thus, annealing temperatures of about 800 °C resulted in an optimum of the electrical properties of the STO films for gate dielectric applications.     

Growth of epitaxial Pr2O3 layers on Si(1 1 1)

The growth of Pr₂O₃ layers on Si(1 1 1) has been studied by X-ray diffraction, Low-energy electron diffraction (LEED) and atomic force microscopy (AFM). Pr₂O₃ starts to grow as a 0.6-nm thick layer corresponding to one unit cell of the hexagonal phase (1 ML). The X-ray results indicate that layers thicker than 0.6 nm do not grow with the hexagonal phase. Growth takes place at a sample temperature of 500–550 °C. Annealing of the monolayer in UHV at a temperature above 700 °C leads to the formation of Pr₂O₃ and PrSi₂ islands. Silicide islands are found only at annealing in UHV and do not occur at annealing in oxygen atmosphere of 10⁻⁸ mbar. The LEED pattern after heating to 730 °C shows a (2×2) and (√3×√3) superstructure and after heating to 1000 °C a (1×5) superstructure occurs. The superstructures seen in the LEED pattern arise from silicide structures in the area between the islands. The silicide remains on the surface and cannot be removed with flashing to 1100 °C. Further deposition of Pr₂O₃ on the surface covered with silicide phases does not lead to growth of ordered layers.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Silicon dioxide deposited by ECR-PECVD for low-temperature Si devices processing

Silicon dioxide films have been deposited at temperatures less than 270 °C in an electron cyclotron resonance (ECR) plasma reactor from a gas phase combination of O₂, SiH₄ and He. The physical characterization of the material was carried out through pinhole density analysis as a function of substrate temperature for different μ-wave power (E_w). Higher E_w at room deposition temperature (RT) shows low defects densities (<7 pinhole/mm²) ensuring low-temperatures process integration on large area. From FTIR analysis and Thermal Desorption Spectroscopy we also evaluated very low hydrogen content if compared to conventional rf-PECVD SiO₂ deposited at 350 °C. Electrical properties have been measured in MOS devices, depositing SiO₂ at RT. No significant charge injection up to fields 6–7 MV/cm and average breakdown electric field >10 MV/cm are observed from ramps I–V. Moreover, from high frequency and quasi-static C–V characteristics we studied interface quality as function of annealing time and annealing temperature in N₂. We found that even for low annealing temperature (200 °C) is possible to reduce considerably the interface state density down to 5 × 10¹¹ cm⁻² eV⁻¹. These results show that a complete low-temperatures process can be achieved for the integration of SiO₂ as gate insulator in polysilicon TFTs on plastic substrates.     

Strain relaxation in SiGe due to process induced defects and their subsequent annealing behavior

Ion implantation and reactive ion etching are known to create defects in silicon which get cured during subsequent annealing operations. In this paper we have reported the annealing behavior of phosphorus implanted into strained SiGe layer at room temperature. The implantation was performed at 155 KeV with a dose of 1×10¹⁴/cm². Post implantation annealing was performed at 600, 700, 800 and 900°C for 10 s in a rapid thermal process furnace. Annealing behavior of defects generated as a consequence of dry etching is also reported. RTP annealing on reactive ion etching (RIE) etched samples were performed at 650, 700, 750 and 800 °C. I–V, C–V and DLTS measurements hint towards the presence of permanent dislocation loops created as a consequence of RIE and implantation causing strain relaxation.     

ICP dry etching of ZnO and effects of hydrogen

Two different plasma chemistries for etching ZnO were examined. Both Cl₂/Ar and CH₄/H₂/Ar produced etch rates which increased linearly with rf power, reaching values of 1200 Å/min for Cl₂/Ar and 3000 Å/min for CH₄/H₂/Ar. The evolution of surface morphology, surface composition, and PL intensity as a function of energy during etching were monitored. The effect of H in ZnO was studied using direct implantation at doses of 10¹⁵–10¹⁶ cm⁻², followed by annealing at 500–700 °C. The hydrogen shows significant outdiffusion at 500 °C and is below the detection limits of SIMS after 700 °C anneals. SEM of the etched features showed anisotropic sidewalls, indicative of an ion-driven etch mechanism.     

High temperature reliability and interfacial reaction of eutectic Sn–0.7Cu/Ni solder joints during isothermal aging

The interfacial reactions and growth kinetics of intermetallic compound (IMC) layers formed between Sn–0.7Cu (wt.%) solder and Au/Ni/Cu substrate were investigated at aging temperatures of 185 and 200 °C for aging times of up to 60 days. After reflow, the IMC formed at the interface was (Cu, Ni)₆Sn₅. After aging at 185 °C for 3 days and at 200 °C for 1 day, two IMCs of (Cu, Ni)₆Sn₅ and (Ni, Cu)₃Sn₄ were observed. The growth of the (Ni, Cu)₃Sn₄ IMC consumed the (Cu, Ni)₆Sn₅ IMC at an aging temperature of 200 °C due to the restriction of supply of Cu atoms from the solder to interface. After aging at 200 °C for 60 days, the Ni layer of the substrate was completely consumed in many parts of the sample, at which point a Cu₃Sn IMC was formed. In the ball shear test, the shear strength decreased with increasing aging temperature and time. Until the aging at 185 °C for 15 days and at 200 °C for 3 days, fractures occurred in the bulk solder. After prolonged aging treatment, fractures partially occurred at the (Cu, Ni)₆Sn₅ + Au/solder interface for aging at 185 °C and at the (Ni, Cu)₃Sn₄/Ni interface for aging at 200 °C, respectively. Consequently, thick IMC layer and thermal loading history significantly affected the integrity of the Sn–0.7Cu/Ni BGA joints.     

Optical dispersion analysis within the IR range of thermally grown and TEOS deposited SiO2 films

SiO₂ thin films, with thickness ranging between approximately 13 and 95 nm, have been thermally grown at 950°C in dry oxygen and chemically vapor deposited at low pressures (0.3 Torr) by decomposition of tetraethylorthosilicate (TEOS) at 710°C, on Si (100) substrates. Dispersion analysis was performed on Fourier transform infrared (FTIR) transmission spectra of these films within the range 900–1400 cm⁻¹. It was found that the spectra were best described within this range, by four Lorentz oscillators located near 1060, 1089, 1165 and 1220 cm⁻¹ almost independent of film thickness. The polarization of the oscillators (proportional to their strength) was found to increase slightly, and their widths to decrease, with film thickness. From the study of the FTIR spectra obtained at room temperature, it was suggested that at this temperature, a considerable number of Si–O–Si angles in these SiO₂ films are distributed in a way expected at higher temperatures and that the distribution of the Si–O–Si angles depends on the thermal history of the film and the method of growth.     

Dielectric tunable properties of (Ba1−xSrx)TiO3 thin films on LaAlO3 substrate

(Ba_1−xSr_x)TiO₃ (1−x=0.8, 0.7, 0.6 and 0.5) thin films were prepared on (0 0 1) LaAlO₃ substrates by sol–gel method. The films were found to be crystallized in preferential (0 0 1) orientation after post-deposition annealing at 750°C for 1.5 h and 1100°C for 2 h in air, respectively. We investigated the dependence of tunability and dissipation factor on annealing temperature and different Ba/Sr ratios. It was found that the tunability increased dramatically and dissipation factor decreased obviously with increasing annealing temperature, and Ba_0.6Sr_0.4TiO₃ thin films annealed at 1100°C for 2 h have a tunability of 46.9% at 80 kV/cm bias filed and a dissipation factor of 0.008 at 1 MHz.     

Hydrogen incorporation, diffusivity and evolution in bulk ZnO

Hydrogen is readily incorporated into bulk, single-crystal ZnO during exposure to plasmas at moderate (100–300°C) temperatures. Incorporation depths of >25 μm were obtained in 0.5 h at 300°C, producing a diffusivity of 8 × 10⁻¹⁰ cm²/V s at this temperature. The activation energy for diffusion is 0.17 ± 0.12 eV, indicating an interstitial mechanism. Subsequent annealing at 500–600 °C is sufficient to evolve all of the hydrogen out of the ZnO, at least to the sensitivity of Secondary Ion Mass Spectrometry (<5 × 10¹⁵ cm⁻³). The thermal stability of hydrogen retention is slightly greater when the hydrogen is incorporated by direct implantation relative to plasma exposure, due to trapping at residual damage.     

Ultra-shallow np junction formed by PH3 and AsH3 plasma immersion ion implantation

Ultra-shallow 28–88 nm n⁺p junctions formed by PH₃ and AsH₃ plasma immersion ion implantation (PIII) have been studied. The reverse leakage current density and intrinsic bulk leakage current density of the diodes are found to be as low as 4.2 nA cm⁻² and 2.4 nA cm⁻², respectively. The influences of pre-annealing condition and the carrier gas on the junction depth and the sheet resistance are also studied. It is found that the increase of H or He content in the PH₃ PIII can slow down the phosphorus diffusion and shallower junction can been obtained. Annealing conditions have pronounced effect on the sheet resistance. It was found that sample annealed at 850 °C for 20 s has reverse results to that annealed at 900 °C for 6 s. For AsH₃ PIII samples, it is observed that two-step annealing is more effective to activate the dopant and a lower reverse current density resulted.     

Investigation of Au/Ti/Al ohmic contact to N-type 4H–SiC

In this study, investigation on Au/Ti/Al ohmic contact to n-type 4H–SiC and its thermal stability are reported. Specific contact resistances (SCRs) in the range of 10⁻⁴–10⁻⁶ Ω cm², and the best SCR as low as 2.8 × 10⁻⁶ Ω cm² has been generally achieved after rapid thermal annealing in Ar for 5 min at 800 °C and above. About 1–2 order(s) of magnitude improvement in SCR as compared to those Al/Ti series ohmic systems in n-SiC reported in literature is obtained. XRD analysis shows that the low resistance contact would be attributed to the formation of titanium silicides (TiSi₂ and TiSi) and Ti₃SiC₂ at the metal/n-SiC interface after thermal annealing. The Au/Ti/Al ohmic contact is thermally stable during thermal aging treatment in Ar at temperature in the 100–500 °C range for 20 h.     

Reliability of 100 nm silicon nitride capacitors in an InP HEMT MMIC process

A reliability study has been conducted on capacitors made with 100 nm of silicon nitride, in an InP HEMT MMIC fabrication process. Special wafers were fabricated, containing 1482 200 × 200 μm² capacitors each, and these were probed automatically. They were subject to ramped-voltage stress and the breakdown voltages recorded. On a typical wafer the vast majority of the breakdown voltages are between 50 and 90 V. In addition, IV curves were measured on a small number of specimens from 0 V up to breakdown. This was done in two regimes: above 25 V with a conventional setup, and below 25 V with an ultra-low-current measurement system. These were done at 25 and 175 °C above 25 V, and at 25 °C only below 25 V. The data were fitted well with a model for the conductivity, consisting of ohmic conduction at low voltages and Frenkel–Poole conduction at high voltages. Parameters of the fits included thermal activation energies, the voltage acceleration factor in the Frenkel–Poole model, and d_eff, the effective thickness of the dielectric at the thinnest point. Analysis invoked the time-dependent dielectric breakdown model, which provides the time to failure as a function of the d_eff, while d_eff can be found from the ramped-voltage measurements. From the 10 wafers that have been probed so far, the mean of the distribution of failure times (at 1.5 V, 40 °C) is above 5 × 10⁷ h, and the distribution becomes insignificant below 2 × 10⁶ h. Further, the probability of failure in 10 years at 1.5 V, 40 °C is much less than 1 in 14,600. This indicates that 100 nm silicon nitride capacitors in this technology have good reliability.