基于GPRS的远程安防监控系统的研究和设计

设计一种以$3C2410为硬件平台和嵌入式Linux为软件平台,基于M35GPRS模块的远程安防监控系统,整个系统围绕图像的采集,传输和显示进行了探讨,阐述了远程安防监控系统中的软硬件处理技术。测试结果表明,该远程安防监控系统具有监控温度,实时传输视频流,通过网页远程控制监控机动作,短信服务和报警等功能。与已有系统相比,该系统把Web服务器和CGI应用到监控机和网页的交互,真正实现了对监控端的远程控制。     

基于ARM7的畜牧养殖智能消毒机器人控制系统设计

电子技术的发展带动机电产品向智能化、人性化的方向发展。本系统采用嵌入式系统以ARM7为远程机器人控制核心,结合GPRS和WIFI无线网络,实现机器人远程控制和工作环境实时监控。安装相应的消毒结构,可以实现远程消毒工作,实现养殖消毒智能化。     

基于ARM的智能家居安防监控系统的设计与实现

介绍了一种以ARM嵌入式开发板为核心、融合因特网通信和GPRS无线通信技术的,智能家居安防监控系统,给出了系统的功能和结构以及硬件原理框图和软件设计思路.该系统由传感器采集信号,摄像头采集图像,经ARM开发板处理后,利用因特网和GPRS模块传输到远程的监控中心.使用Boa嵌入式Web服务器和SQLite数据库搭建远程监控系统,用户通过点击网页上的按钮远程发送控制命令.实验测试表明,该系统不仅有效地实现了快速报警、远程监控功能,还实现的图像的抓拍、打包下载等功能,满足远程监控的设计要求.     

家庭火灾检测报警系统

本设计采用液晶温度感应器做温度检测,用MQ-2烟雾传感器做可燃气体检测,将家庭火灾检测、燃气泄露报警系统相结合,实现对家庭常见火灾威胁进行监控并报警。系统报警方式为蜂鸣器蜂鸣报警和短信报警,实现进程报警与远程报警结合。短信报警模块可以存入六个报警号码,针对不同险情分别发送对应内容的报警信息。本系统以生活辅助的身份,帮助用户检测环境安全状况,在险情发生时及时提醒业主做出相关行动,最大限度的减少家庭损失。     

智能家庭监控报警系统的设计

设计了智能家庭监控报警系统以实现对家居安全的实时监控。系统采用了单片机技术、WIFI、蓝牙和GSM/GPRS网络进行设计,能够通过手机接受报警信息和远程指令;同时引入多种传感器和继电器实现了对家中基本情况、安全隐患等的远程控制。实验结果表明,所设计的系统能够实现安全、便捷的智能家居远程监控,具有较高的可用性和可靠性。     

基于无线传输的远程家庭安防系统研究

文章提出了一种基于无线传输的远程家庭安防系统的设计和实现。由于现在社会生活节奏快,为让年轻人能安心工作,文章通过对家庭环境进行远程监控,用户家庭一旦出现有盗窃、燃气泄漏、水管破裂和火灾等险情时,通过GSM无线传输的方式向用户及时发送短信,同时用户可以采用自动和手动两种方式实现家庭的远程控制。     

基于GPRS振动光缆周界报警系统在水中安防应用

介绍了振动光缆报警系统的组成及原理。并在此基础上,应用GPRS技术,设计了基于GPRS的振动光缆周界报警系统。利用GPRS的短消息功能,实现无线远程报警功能。文中描述了应用GPRS模块的设计与应用,根据应用环境的不同采取不同布防方式,而由于采用无线传输报警,系统布防简单、便于施工。该系统已成功应用于2010年广州亚运会水下安防系统中,通过用户测试验收、系统运行可靠、漏报警率低、虚警率低。     

基于ARM及GPRS的远程入侵监控报警系统的设计

为了实现远程入侵监控报警的需求,设计了一种基于MMS功能的红外入侵检测监控报警系统,该系统把红外技术、彩信技术、无线通信技术充分结合起来,实现了将监控现场采集的入侵者图片通过GPRS网络以彩信的形式发送到用户手机的功能,使用户远离家中也可以实时掌控家中的情况。     

基于Home bus协议的电话远程监控模块的设计

文章介绍了基于Homebus协议的电话远程监控模块及其软硬件设计平台。该电话模块是家庭总线系统与用户之间的接口 ,采用电话线作为传输通道 ,具有自动拨号报警功能。其电路设计合理 ,结构紧凑 ,报警过程迅速准确。按键式IVR技术充分考虑了人性化设计 ,大大方便用户操作     

GPRS技术在小电厂远程监控系统中的应用

根据小电厂实行无人值班监管的发展要求,设计一种基于GPRS技术的小电厂远程监控系统。以LPC2378为CPU的监测节点采集监控参数,由GPRS模块经过GPRS网络传给远程监控中心进行集中显示、数据处理。监控中心通过数据分析,给出设备故障报警、越限报警等。实验结果表明:该系统采集到的数据真实、可靠,满足小电厂无人值班的要求。该系统实现远程无线监管,监控范围广,可减少电厂管理人员、提高值班人员的工作效率50%以上。     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

A stereo audio sigma-delta A/D-converter

A stereo sigma delta A/D-converter for audio applications is presented. In this converter, two identical cascaded fourth-order sigma-delta modulators and a sophisticated multistage linear-phase FIR decimation filter with oversampling ratio of 64 are implemented on the same die. The analog part is designed to operate at a low voltage with a low power consumption. Techniques to achieve simultaneously a high performance and a low power consumption are discussed in details. The minimum stopband attenuation of the decimator is more than 120 dB and the passband ripple of the overall converter is less than 0.0003 dB. The first decimation stage is a special tapped comb filter, whereas the remaining stages are realized without general multipliers by simultaneously implementing all the filter coefficients by using special bit-serial networks. For the integrated overall stereo converter, the power consumption and the signal-to-noise ratio are 180 mW and 97 dB (85 mW and 95 dB) for a 5 V (3 V) power supply. The circuit die area is only 4.7 mm×5.5 mm using a 1.2 μm double-poly BiCMOS process