基于CMOS对数域积分器的小波变换模拟VLSI实现

提出了一种基于CMOS对数域积分器的连续Marr小波变换模拟VLSI实现方法.构造了Marr母小波时域逼近函数模型,用Levenbery-Marquardt非线性最小二乘法求解模型参数最优解,得到母小波逼近函数.设计了以CMOS对数域积分器为积木块的小波变换电路,该电路由冲激响应为母小波逼近函数及其伸缩函数的滤波器组构成,滤波器组采用低灵敏度的IFLF结构进行综合.SPICE仿真结果表明该方法的可行性.     

用对数域电流模式电路实现连续小波变换

本文提出了用对数域电路实现连续小波变换的一种方法.利用复解调技术将设计带通滤波器组转化为设计相对简单的低通滤波器组问题,给出了分解与重构的系统流程.设计并分析了对数域电流控制振荡电路,对数域积分器和高斯滤波器等主要的模拟电路.     

Analog Implementation of Wavelet Transform in Switched-Current Circuits with High Approximation Precision and Minimum Circuit Coefficients

This paper presents a novel procedure for analog implementation of wavelet transform in switched-current (SI) circuits. An improved hybrid PSO–SQP optimization is employed to precisely approximate the impulse response of a filter to the wavelet base function in time domain. The SI first- and second-order section circuits with minimum coefficients are designed based on infinite-impulse-response digital filter technology. Cascode techniques are occupied to reduce the effects of parasitic elements. Based on these SI first- and second-order section circuits, a parallel wavelet circuit structure is presented to synthesize the approximated wavelet base function. By adjusting the switch clock frequency, the wavelets at different scales can be realized. The Gaussian wavelet is selected as an example to illustrate the design procedure. Simulation results demonstrate the feasibility of the proposed procedure for analog wavelet transform in SI circuits.     

数模混合电路实现一维模拟小波变换芯片

整个电路采用标准CMOS工艺,采取模块化设计的方法,把数字频率发生器和模拟滤波器部分分开设计。数字频率发生器采用直接数字综合(DDS)的方式,来产生5种不同中心频率(10个通道),简化了传统模拟压控振荡器(VCO)的设计,提高了频率发生器的灵活性;根据精度要求,模拟高斯低通滤波器采用5阶低通滤波器来进行逼近。并论述和讨论了一种用数字和模拟混合集成电路来实现一维模拟输入的连续小波变换(CWT)芯片的方法。     

A simple structure wavelet transform circuit employing function link neural networks and SI filters

Signal processing by means of analog circuits offers advantages from a power consumption viewpoint. Implementing wavelet transform (WT) using analog circuits is of great interest when low-power consumption becomes an important issue. In this article, a novel simple structure WT circuit in analog domain is presented by employing functional link neural network (FLNN) and switched-current (SI) filters. First, the wavelet base is approximated using FLNN algorithms for giving a filter transfer function that is suitable for simple structure WT circuit implementation. Next, the WT circuit is constructed with the wavelet filter bank, whose impulse response is the approximated wavelet and its dilations. The filter design that follows is based on a follow-the-leader feedback (FLF) structure with multiple output bilinear SI integrators and current mirrors as the main building blocks. SI filter is well suited for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by the clock frequency of the circuit with the same system architecture. Finally, to illustrate the design procedure, a seventh-order FLNN-approximated Gaussian wavelet is implemented as an example. Simulations have successfully verified that the designed simple structure WT circuit has low sensitivity, low-power consumption and litter effect to the imperfections.     

Analog VLSI implementation of wavelet transform using switched-current circuits

For applications requiring low-voltage low-power and real-time processing, a novel scheme for the VLSI implementation of wavelet transform (WT) using switched-current (SI) circuits is presented. SI circuits are well suited for these applications since the dilation constant across different scales of the transform can be implemented, and controlled by both the aspect-ratio of the transistors and the clock frequency. The quality of such implementation depends on the accuracy of the corresponding wavelet approximation. First, an optimized procedure based on differential evolution algorithm (DE) is applied to approximate the transfer function of a linear steady-state system whose impulse response is the required wavelet. The proposed approach significantly improves the accuracy of approximation wavelets. Next, the approximation of time-domain wavelet function is implemented by the SI analog filters. Finally, the design of the complete SI filter based on first-order and biquad section as main building block is detailed. Simulations demonstrate the performance of the proposed approach to analog WT implementation.     

Low-Voltage Log-Domain Complex Filters

Two systematic methods for designing low-voltage log-domain complex filters are introduced in this paper. The first one is based on the transposition of the signal flow graph representation of the linear-domain complex leapfrog prototype filter to the corresponding one in the log-domain. The last one is based on the transposition of the wave equivalents of the elements of the complex passive prototype filter to the corresponding log-domain complex equivalents. Both transpositions are performed by employing an appropriate set of complementary operators that facilitates the derivation of low-voltage log-domain filter configurations. Two design examples are given, where a 12th-order log-domain complex transfer function is realized in order to fulfill the Bluetooth specifications. The derived log-domain filter structures operate at a single 1.2-V-power supply-voltage, and their behavior was evaluated through simulation results. In addition, a comparison concerning important quality factors of both of the proposed structures is performed, and the obtained results are further discussed.      

A 19 nW analogue CMOS log-domain 6th-order Bessel filter without E-minus cells

This paper contributes to the field of low-power high-order CMOS log-domain filters by: (a) suggesting a log-domain synthesis path which bypasses the need for E-minus cells and (b) by assessing the practicality of the proposed synthesis path by means of a 6th-order CMOS log-domain Bessel filter fabricated in the commercially available AMS 0.35 μm process. Measured results from the 19 nW, 8-200 Hz, 940 μm² Bessel filter chip confirm the validity of the proposed approach. The filter reported here is particularly useful for biomedical instruments such as portable ECG devices and Pulse-oximeters.     

Detection of Cardiac Signal Characteristic Point Using Log-Domain Wavelet Transform Circuits

To meet the requirement of low power consumption in biomedical implantable pacemaker applications, a novel method based on balanced log-domain wavelet transform (WT) circuits has been developed for detecting QRS complexes of cardiac signals. By using a hybrid particle swarm optimization algorithm (PSO) combined with sequential quadratic programming, an excellent approximation of the first derivative of a Gaussian wavelet is achieved. The WT circuits are composed of filters whose impulse response is the approximation of the Gaussian wavelet. The WT filter design is based on a time inverse follow-the-leader feedback structure with class-AB balanced log-domain integrators as the main building blocks. HSPICE simulation shows that the power consumption is only 62 nW per scale for a 1.2 V supply, and the dynamic range is 86 dB for 2% total harmonic distortion. The high accuracy of the QRS complex detection method has been validated using the MIT-BIH database. This work was supported by the National Natural Science Foundation of China under Grant No. 50677014, Doctoral Special Fund of Ministry of Education under Grant No. 20060532002, High-Tech Research and Development Program of China (No. 2006AA04A104), the Program for New Century Excellent Talents in University of China (NCET-04-0767), and the Foundation of Hunan Provincial Science and Technology (06JJ2024).     

低电压全BJT高阶对数滤波器设计

提出了一种1.2 V低电源电压全BJT任意阶低通对数滤波器的设计方法.该方法是由传输函数直接设计低通对数域滤波器,得到最优的BJT跨导线性单元和滤波器系统状态空间后,利用最优状态空间描述滤波器系统,对微分方程中的每一项,使用最优BJT跨导线性单元设计其对应的电路,进行组合,从而得到低通对数滤波器,实现了不同阶数、不同纹波的切比雪夫低通滤波器,理论分析和Pspice实例仿真表明,该方法能最优地实现所需电路的设计,具有电路简洁和低电压的特点.     

A micropower class-AB CMOS log-domain filter for DECT applications

This paper presents a micropower second-order low-pass filter using the log-domain principle and integrated in a 0.35-μm CMOS process. It has been designed as an antialiasing filter for a DECT transceiver with a 45-kHz nominal cutoff frequency. The circuit uses transistors biased in weak inversion without requiring separate wells. It operates at 1.5-V supply voltage and its current consumption is 8 μA in idle mode. The log-domain filter is implemented with an on-chip conditioner which allows class-AB operation. It can process input currents at 5 kHz that are 25 times larger than the 200-nA bias current. Measurements up to 500 times the bias current have been done, since at 1 kHz the input current is only limited by the supply voltage     

基于对数域的连续小波变换处理电路

提出了一种新型的连续小波变换处理电路.电路中采用复解调技术实现小波变换,对变换系数进行了模数转换,可以与数字处理芯片接口,实现了信号的实时处理.电路完全采用对数域电流模式实现.对电路的主要模块进行了分析,仿真结果显示电路能在低电压低功率时得到宽动态范围的运用.     

基于信号流图的任意阶对数域滤波器设计

本文给出了一种基于信号流图的任意阶对数域电流模式滤波器的通用设计方法.用该方法产生的,n阶滤波器由2n个对数单元电路和n个接地电容组成,易于集成.在此基础上给出了三阶Butterworth滤波器的设计实例及其PSpice计算机模拟结果.     

Low Voltage Micropower Log-Domain Filters

A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-m mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm² without the i/o pads     

基于小波分解和BP网络模拟电路故障诊断研究

为了高效、准确地对模拟电路故障进行诊断,采用了一种基于小波多层分解和BP神经网络相结合的模拟电路故障诊断方法。该法利用了多层小波分解优异的时频特性来提取故障特征参数,结合了BP网络强大的非线性分类能力和快速的收敛特性。将该方法应用到模拟带阻滤波器单一软故障诊断中,仿真结果表明该方法是有效的,而且具有比传统BP网络方法的学习收敛速度快得多,诊断正确率高的特点。     

A 1 V Micropower FGMOS Class AB Log-Domain Filter

A novel first-order CMOS log-domain filter is presented. The internal voltage swing compression due to its instantaneous voltage companding nature, together with the use of Floating-Gate MOS transistors and its class AB differential topology, allows operation with a single 1 V supply while maintaining at the same time a large input range. Moreover, operation in weak inversion leads to very low power consumption. The filter can be tuned in more than one decade through its bias currents. Simulation and measurement results of an experimental prototype fabricated in a 0.8 μm CMOS technology demonstrate on silicon the feasibility of the proposed technique, which can be readily extended to higher-order filters.     

Time-varying discrete-time signal expansions as time-varying filter banks

The time-varying discrete-time signal expansion was analysed based on the theory of time-varying filter banks in detail. A general definition of time-varying discrete-time wavelet transforms is provided. Usually, a time-varying discrete-time signal expansion can be implemented using a time-varying filter bank. Using the time-varying filter bank theory, the authors developed a useful algorithm to calculate the dual basis function in a biorthogonal time-varying discrete-time signal expansion. Example is given to show the usage of the algorithm. In the last part, the authors provide a detailed analysis of the general time-varying discrete-time wavelet transform. Some useful properties of the time-varying discrete-time wavelet transform including their proofs are given. The relationship between the tree-structured implementation and the non-uniform filter bank implementation is discussed.     

Frequency-Domain Design of Overcomplete Rational-Dilation Wavelet Transforms

The dyadic wavelet transform is an effective tool for processing piecewise smooth signals; however, its poor frequency resolution (its low Q-factor) limits its effectiveness for processing oscillatory signals like speech, EEG, and vibration measurements, etc. This paper develops a more flexible family of wavelet transforms for which the frequency resolution can be varied. The new wavelet transform can attain higher Q-factors (desirable for processing oscillatory signals) or the same low Q-factor of the dyadic wavelet transform. The new wavelet transform is modestly overcomplete and based on rational dilations. Like the dyadic wavelet transform, it is an easily invertible 'constant-Q' discrete transform implemented using iterated filter banks and can likewise be associated with a wavelet frame for L₂(R). The wavelet can be made to resemble a Gabor function and can hence have good concentration in the time-frequency plane. The construction of the new wavelet transform depends on the judicious use of both the transform's redundancy and the flexibility allowed by frequency-domain filter design.     

Bursting Hodgkin–Huxley model-based ultra-low-power neuromimetic silicon neuron

This paper presents a compact, ultra-low-power implementation of the bursting Hodgkin?CHuxley model-based silicon neuron. The Hodgkin?CHuxley model is a neuron imitation that consists of two calcium current channels, a potassium current channel and a leakage current channel. In the proposed architecture, the calcium and the potassium current channels have been implemented using a sigmoid-function structure, a log-domain filter, and a linear transconductor. Different neuronal signals can be generated by changing the value of the capacitor in the log-domain filter. The proposed silicon neuron is capable of generating four different outputs, namely, spiking, spiking with latency, bursting, and chaotic signals. Ultra-low-power consumption is achieved by current-reuse technique and subthreshold region operation of MOSFETs. The circuit is designed using 0.13???m standard CMOS process. The entire design uses 43 transistors, with a total power consumption of only 43?nW.