共查询到20条相似文献,搜索用时 484 毫秒
1.
The performance of n-MOSFETs with furnace N2O-annealed gate oxides under dynamic Fowler-Nordheim bipolar stress was studied and compared with that of conventional oxide (OX). Time-dependent dielectric breakdown at high frequency was shown to be improved for the N2 O-annealed devices compared with that for devices with OX. In addition, a smaller V t shift after stress was found for nitrided samples. The shift decreased with increasing stressing frequency and annealing temperature. Measurements of both G m and D it revealed a peak frequency at which the degradation was the worst. A hole trapping/migration model has been proposed to explain this 相似文献
2.
The influence of gate edge shape on the degradation in hot-carrierstressing of n-channel transistors
The hot-carrier properties of planar and graded gate structures (upturning of the gate edge in the gate overlap region) of n-MOS transistors were examined. It was found that the type of degradation suffered by each type of device depends on the shape of the gate edge. This is interpreted in terms of the degree of gate control of the gate over the region in which the damage takes place in the different devices. The nongraded gate (NGG) devices degrade chiefly by a V t shift, whereas the graded gate (GG) devices show a pronounced transconductance decay, with practically no V t shift. It is suggested that the damage is situated in the gate overlap region, and that the different degradations result from a weaker field control of the gate over the degraded region leading to a series resistance type of effect in the case of the GG structure. This is supported by two-dimensional simulations 相似文献
3.
Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V d=5.5 V and gate voltage V g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG m and threshold voltage shift ΔV t, do not occur at the same V g. As well, ΔK t is very small for the V g <V d stress regime, becomes significant at V g≈V d, and then increases rapidly with increasing V g, whereas ΔG m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress 相似文献
4.
The authors report on the off-state gate current (I g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I g at drain voltages as low as 4 V and an I g injection efficiency reaching 0.8, as compared to 8.5 V and 10-7 in SiO2 devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure 相似文献
5.
It is reported that fluorine can jeopardize p+-gate devices under moderate annealing temperatures. MOSFETs with BF2 or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 12 cm-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I -V characteristics of PMOSFET with fluorine incorporated p+-gate revealed that the long gate-length device had abnormal abrupt turn-on I d-V g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I d-V g characteristics associated with long-gate-length p+-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C -V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p+-gate devices is presented. The incorporation of fluorine in the p+ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states 相似文献
6.
The circuit performance of CMOS technologies with silicon dioxide (SiO2) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V GS⩽5 V and B DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO2 inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μp (hole mobility) of RONO p-channel devices. At 300 K, μp(RONO) is 14-8% smaller than μp(SiO2) over the entire range of gate biases, while μn(RONO) (electron mobility of n-channel RONO devices) is also smaller than μn(SiO2) and reaches only 96% of μn(SiO2) at V GS=5 V. At 100 K, μn(RONO)/μn (SiO2) at V GS=5 V is increased to 1.10, however, μp(RONO)/μp(SiO2) at V GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO2 inverters 相似文献
7.
Hsing-Huang Tseng Tobin P.J. Baker F.K. Pfiester J.R. Evans K. Fejes P.L. 《Electron Devices, IEEE Transactions on》1992,39(7):1687-1693
Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V TP) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V TP shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO2/Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V TP shift 相似文献
8.
Hida H. Tsukada Y. Ogawa Y. Toyoshima H. Fujii M. Shibahara K. Kohno M. Nozaki T. 《Electron Devices, IEEE Transactions on》1989,36(10):2223-2230
The authors describe a novel design concept for enhancement (E) and depletion (D) mode FET formation using i-AlGaAs/n-GaAs doped-channel hetero-MISFET (DMT) and a novel self-aligned gate process technology for submicrometer-gate DMT-LSIs based on E/D logic gates. 0.5-μm gate E-DMTs (D-DMTs) with a lightly doped drain (LDD) structure show an average V t of 0.18 (-0.46) V, a V t standard deviation of 22.6 (24.9) mV, and a maximum transconductance of 450 (300) mS/mm. The V t shift is less than 50 mV with a decrease in gate length down to 0.5 μm. The gate forward turn-on voltage V f is more than 0.9 V, i.e. about 1.6 times that for MESFETs. This superiority in V f, preserved in the high-temperature range, leads to an improvement in noise margin tolerance by a factor of three. In addition, 31-stage ring oscillators operate with a power consumption of 20 (1.0) mW/gate and a propagation delay of 4.8 (14.5) ps/gate. Circuit simulation based on the experimental data predicts 140 ps/gate and 1 mW/gate for DMT direct-coupled FET logic circuits under standard loading conditions. DMTs and the technology developed here are very attractive for realizing low-power and/or high speed LSIs 相似文献
9.
Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V d =8 V and V g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V b), having a power-law gradient of 0.5 for V b=0 V and 0.3 for V b=-9 V. Investigation of the type of damage resulting from stressing shows that at V b=0 V, interface state generation results, while at V b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions 相似文献
10.
Chen Ih-Chin Choi Jeong Yeol Hu Chenming 《Electron Devices, IEEE Transactions on》1988,35(12):2253-2258
The correlation between channel hot-carrier stressing and gate-oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate-oxide integrity even when other parameters (e.g., ΔV T and ΔI D) have become intolerably degraded. In the extreme cases of stressing at V G≈V T with measurable hole injection current, however, the oxide charge to breakdown decreases linearly with the amount of hole fluence injected during the channel hot-hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an ESD (electrostatic discharge) failure mechanism 相似文献
11.
Hot-carrier degradation of W gate PMOSFETs, which are surface-channel devices because of the work function of W, has been investigated in comparison with polycide (WSix/n+ poly-Si) ones. In W gate PMOSFETs, transconductance g m and threshold voltage V th decrease on the drain avalanche hot-carrier (DAHC) stress, and Δg m /g m0 and ΔV th become minimum at V G≅V D/2. By using the charge-pumping technique, it is found that, after stressing at the same stress condition, the interface state density of W gate devices is about 10 times larger than that of polycide ones but the densities of trapped electrons are almost equal. These results indicate that the difference of hot-carrier degradation between W and polycide gate devices is mainly caused by the difference of the interface state density 相似文献
12.
Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V DB =55 V (R sp=0.2 mΩ-cm2, k D=5.7 Ω-pF) and V DB=35 V (R sp=0.15 mΩ-cm2, k D =4.3 Ω-PF) were developed where V DB is the drain-source avalanche breakdown voltage, R sp is the specific on-state resistance, and k D=R spC sp is the input device technology factor where C sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model 相似文献
13.
The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN2 temperatures on n-channel FETs for both ONO and conventional SiO 2 films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO2 devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel 相似文献
14.
Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I sub condition (V g =0.5 V d). However, in the high-gate-bias region (V g=V d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V g>V d), this current-crowding effect in the diagonal transistor can be a serious reliability concern 相似文献
15.
The switching time of a-Si thin-film transistors (TFTs) was measured. During pulsed operation there are dynamic changes of threshold voltage (V t) and gate capacitance which occur mostly on a time scale ranging from microseconds to milliseconds. These can be qualitatively explained in terms of the fraction of the induced channel charge which is trapped in deep states in the semiconductor, and its spatial distribution. The value of V t can decrease by a much as 3 V during a pulse and also depends on the duty cycle. In pulsed operation, V t is always less than the static value; hence, the current output will be higher than calculated from the static characteristics and will depend on the duty cycle. The effective mobility remains nearly constant with changes of operating cycle. The change in source-gate capacitance confirms the inward diffusion of the trapped charge 相似文献
16.
《Electron Devices, IEEE Transactions on》1990,37(1):153-158
The fabrication of a silicon heterojunction microwave bipolar transistor with an n+ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V CE=6 V, I c=15 mA), and an emitter Gummel number G E of about 1.4×1014 Scm-4. From the measured S parameters, a cutoff frequency f t of 5.5 GHz and maximum oscillating frequency f max of 7.5 GHz at V CE=10 V, I c=10 mA are obtained 相似文献
17.
Oxide charge buildup during channel-hot-carrier (CHC) injection was investigated by the use of a modified charge-pumping technique. An apparent `turnaround' effect in local oxide charge density during low gate voltage (V T<V g<1/2 V d) stressing was observed. It can be explained by the dynamic evolution of the damage location caused by the continuous changes in the electric field distribution during CHC. Dependence on channel length is also presented 相似文献
18.
Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n -channel MOSFETs with various LDD n- doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n+ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n- doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n -channel MOSFETs induced by AC stress was rather severe 相似文献
19.
Marchetaux J.-C. Bourcerie M. Boudou A. Vuillaume D. 《Electron Device Letters, IEEE》1990,11(9):406-408
The evolution of the gate current-voltage (I g- V gs) characteristics of n-MOSFETs induced by DC stresses at different gate voltage over drain voltage (V ds ) ratios is studied by the floating-gate (FG) measurement technique. It is shown that the I g-V gs curves are always lowered after aging, and that the kinetics are dependent on the aging conditions. A time power law is representative of the V gs=V ds case. It is demonstrated that electron traps are created in the oxide by both hot-hole and hot-electron injection stresses. They are not present in the devices before aging. They can be easily charged and discharged by short electron and hole injections, respectively 相似文献
20.
Busta H.H. Pogemiller J.E. Zimmerman B.J. 《Electron Devices, IEEE Transactions on》1993,40(8):1537-1542
The field at the tip of a field emitter triode can be expressed by E =βV g+γV c, where V g and V c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, γV c<<βV g. The-device is operated in the gate-induced field emission mode and the corresponding I -V c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I -V c and transconductance g m-V g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly 相似文献