Secure Hardware Implementation of ARIA Based on Adaptive Random Masking Technique

The block cipher ARIA has been threatened by side‐channel analysis, and much research on countermeasures of this attack has also been produced. However, studies on countermeasures of ARIA are focused on software implementation, and there are no reports about hardware designs and their performance evaluation. Therefore, this article presents an advanced masking algorithm which is strong against second‐order differential power analysis (SODPA) and implements a secure ARIA hardware. As there is no comparable report, the proposed masking algorithm used in our hardware module is evaluated using a comparison result of software implementations. Furthermore, we implement the proposed algorithm in three types of hardware architectures and compare them. The smallest module is 10,740 gates in size and consumes an average of 47.47 μW in power consumption. Finally, we make ASIC chips with the proposed design, and then perform security verification. As a result, the proposed module is small, energy efficient, and secure against SODPA.     

Software and Hardware Techniques for SEU Detection in IP Processors

In the recent years both software and hardware techniques have been adopted to carry out reliable designs, aimed at autonomously detecting the occurrence of faults, to allow discarding erroneous data and possibly performing the recovery of the system. The aim of this paper is the introduction of a combined use of software and hardware approaches to achieve a complete fault coverage in generic IP processors, with respect to SEU faults. Software techniques are preferably adopted to reduce the necessity and costs of modifying the processor architecture; since a complete fault coverage cannot be achieved, partial hardware redundancy techniques are then introduced to deal with the remaining, not covered, faults. The paper presents the methodological approach adopted to achieve the complete fault coverage, the proposed resulting architecture, and the experimental results gathered from the analysis of the fault injection campaigns.     

High-Value Design Techniques for Mitigating Random Defect Sensitivities

Today's sophisticated design-for-manufacturability (DFM) methodologies provide a designer with an overwhelming amount of choices, many with significant costs and unclear value. The technology challenges of subwavelength lithography, new materials, device types/sizes, etc., can mask the underlying random defect yield contribution which ultimately dominates mature manufacturing, and the distinction between technology limitations and process excursions must also be understood. The best DFM strategy fully exploits all of the available techniques that mitigate a design's sensitivity to random defects where the value is clearly quantifiable, yet few designers seize this opportunity. This paper provides a roadmap through the entire design flow and gives an overview of the various options.      

Security Vulnerabilities: From Analysis to Detection and Masking Techniques

This paper presents a study that uses extensive analysis of real security vulnerabilities to drive the development of: 1) runtime techniques for detection/masking of security attacks and 2) formal source code analysis methods to enable identification and removal of potential security vulnerabilities. A finite-state machine (FSM) approach is employed to decompose programs into multiple elementary activities, making it possible to extract simple predicates to be ensured for security. The FSM analysis pinpoints common characteristics among a broad range of security vulnerabilities: predictable memory layout, unprotected control data, and pointer taintedness. We propose memory layout randomization and control data randomization to mask the vulnerabilities at runtime. We also propose a static analysis approach to detect potential security vulnerabilities using the notion of pointer taintedness.     

Hardware Generation of Random Single Input Change Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost.It has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. It has also been shown that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non robust tests are under consideration; the experimental results were based on a software generation of RSIC sequences that are easily generated.Obviously, a hardware RSIC generation providing similar results can be obtained. However, this hardware generator must be carefully designed. In this paper, it is explained what are the criteria which must be satisfied for this purpose. A solution is proposed and illustrated with an example. Then, it is shown that a bad result may be obtained if one of these criteria is not satisfied.     

Hardware Architecture for Guessing Random Additive Noise Decoding Markov Order (GRAND-MO)

Journal of Signal Processing Systems - Communication channels with memory are often sensitive to burst noise, which drastically reduces the decoding performance of standard channel code decoders,...     

Hybrid Random Number Generation Architecture for Mobile Registration Controller: A Reconfigurable Hardware Realization

Mobile phones have become one of the mostly used gadgets in the world. The number of devices being used has been increasing tremendously and the concern for signal connectivity has been growing everyday. In this work, a mobile phone location registration model has been proposed using a hybrid random number generator (HRNG). Traffic of the cellular devices during the successive location registration with base station can be managed by incorporating a HRNG which produces different delays in different mobile phones. This HRNG was designed using ring oscillator, PLL and cellular automata. The developed HRNG was utilized to create non-overlapping pulses on Cyclone II FPGA EP2C20F484C7 which depict a part of mobile registration controller hardware. The proposed scheme utilized 1616 combinational functions and 1003 registers with a total power dissipation of 69.96 mW. The HRNG was analyzed with restart, entropy and NIST randomness analyses. The capability of mobile registration architecture was analyzed with correlation and random distribution analyses.

     

长周期硬件高速任意位数随机数产生器

本文介绍的随机数产生方法利用m序列所特有的性质,完全采用硬件电路产生,产生速率快.若随机数为16Bit,则速率可达50MHz/16=3.125MHz;随机数周期长,若利用24级移位寄存器产生m序列,则16Bit随机数的周期至少为2~(24)/16=2~(20).因此该方法产生的伪随机数可以再现.由于完全利用硬件产生,因此该方法产生速率快,不占用CPU和存贮单元,且能保证足够长的周期.经过均匀性和独立性的检验,该方法产生的伪随机数紧密地近似于理想的随机数.     

行为级硬件描述语言XHDL的模拟机制

本文介绍了一种集成电路行为级硬件描述语言ＸＨＤＬ，以及利用ＸＨＤＬ如何进行电路的高层次描述，在此基础上着重讨论了ＸＨＤＬ的模拟机制。     

A Multibeam Packet Satellite Using Random Access Techniques

The performance of a multibeam packet satellite using ALOHA type random access techniques is studied. The satellite provides either no buffer or an infinite buffer for successful packets on the uplink channels. A TDMA frame is organized in accordance with the traffic demand from each area. System throughput and packet delay have been successfully obtained. Aiming at improving the performance of the system, three different protocols are introduced and studied in the zero buffer case. It is demonstrated, through examples, that satisfactory system performance can be obtained using an appropriate protocol. However, system performance can also be severely degraded if the transition time for the satellite transponder to switch from one zone to another is not negligible. In this case, the performance can be restored via the use of a buffer of sufficiently large size.     

Frequency-Response Masking Filters Based on Serial Masking Schemes

In this paper, computationally efficient filter structures based on the frequency-response masking (FRM) technique are proposed for the synthesis of arbitrary bandwidth sharp finite impulse response (FIR) filters. A serial masking scheme is introduced in the new structures to perform the masking task in two stages, which reduces the complexity of the masking filters. Compared to the original FRM and interpolated FIR-FRM (IFIR-FRM) structures, the proposed structures achieve additional savings in terms of numbers of arithmetic operations.     

高速数据采集系统中的差拍和随机采样技术

提出一种为解决高频、宽带周期信号的数据采集而发展起来的差拍和随机等效采样技术。介绍了用产生分频脉冲和步进脉冲的方法实现的差拍采样,给出了随机采样系统的实现原理、关键技术以及正负延迟触发的控制技术。     

移相掩模技术

对光学微细加工技术中骤然崛起的移相掩模技术,从原理、掩模种类以及尚待解决的问题等方面作了较为详尽的介绍。 该技术由于大幅度提高分辨率、空间相干性和增大焦深,目前已用于0.2～0.3μm LSI的设计。     

Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method

We present an automated methodology for producing hardware-based random number generator (RNG) designs for arbitrary distributions using the inverse cumulative distribution function (ICDF). The ICDF is evaluated via piecewise polynomial approximation with a hierarchical segmentation scheme that involves uniform segments and segments with size varying by powers of two which can adapt to local function nonlinearities. Analytical error analysis is used to guarantee accuracy to one unit in the last place (ulp). Compact and efficient RNGs that can reach arbitrary multiples of the standard deviation sigma can be generated. For instance, a Gaussian RNG based on our approach for a Xilinx Virtex-4 XC4VLX100-12 field-programmable gate array produces 16-bit random samples up to 8.2 sigma. It occupies 487 slices, 2 block-RAMs, and 2 DSP-blocks. The design is capable of running at 371 MHz and generates one sample every clock cycle.     

等离子刻蚀铬膜的研究

本文叙述等离子刻蚀铬膜的基本原理,用空气携带四氯化碳为气源,在高频电场作用下产生等离子体.实验证明,该等离子体能有效地刻蚀铬膜,获得较理想的微细图形.     

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages

Sequential Automatic Test Pattern Generation is extremely computation intensive and produces acceptable results only on relatively small designs. Hierarchical approaches that target one module at a time and use ad-hoc abstractions for the rest of the design, have shown promising results in reducing the test generation complexity. This paper develops an elegant theoretical basis, based on program slicing, for hierarchical test generation. The technique to systematically obtain a constraint slice for each embedded module under test within a design, is described in detail. The technique has been incorporated in an automated tool for Verilog designs, and results on large benchmark circuits show the significant benefits of the approach.     

结合时变滤波和时频掩码的语音增强方法

本文提出了一种结合鲁棒时变滤波和时频掩码的语音增强方法。首先在带噪语音的时频域中,结合图像处理方法估计出初始瞬时频率信息。然后基于该瞬时频率信息,利用鲁棒时变滤波算法构建降噪后的语音信号。最后根据重构语音的时频特征预测时频掩码。该掩码在带噪语音的时频域中能够有效地保留语音成分且抑制噪声成分,从而达到语音增强的目的。实验结果表明,在几种常见背景噪声环境下,所提语音增强算法在抑制背景噪声干扰、提升语音整体质量方面表现良好,尤其是在低信噪比环境下具有明显的优势。      

相控阵天线适当随机馈相法对相位量化瓣的抑制

适当随机馈相法,对于减小相控阵天线波束指向误差,确有成效,已经作了比较.本文对改进型适当随机馈相法在降低相位量化所引起的寄生副瓣电平方面的作用作了分析,用计算机模拟计算,并进行了比较.结果表明,适当预加相位法性能较差,适当相位误差均值为零法和适当二可能值法的性能相近,比适当预加相位法略胜一筹.     

随机数的捕获及其基于Web的应用

在计算机程序应用中，很多应用是随机的，因此，产生随机数并捕获这些随机数是非常重要的，本文通过一个具体的例子给出了一个如何捕获随机数并利用捕获的随机数进行WEB应用的实际解决方案，效果良好。