System-level test and yield improvement for optoelectronic-VLSI chips

Some of the unique issues involved in testing transmitter and receiver circuits for optoelectronic-very-large-scale-integrated (OE-VLSI) applications are reviewed. In particular, the problem of testing OE-VLSI chips prior to optoelectronic device integration is outlined. Based on circuit-level approaches such as fault sensitization and novel system-level testing methodologies, the first OE-VLSI chip with testable transmitters, receivers and digital circuitry was designed in 0.35-/spl mu/m CMOS. The operation of the ASIC was verified experimentally and a fault-coverage greater than 80% is obtained, for a test time in the hundreds of microseconds range. Yield improvements ranging from 10% to 25% are predicted.     

Optical broadcast and clock distribution for multi-chip-modules

In this letter, we report a new architecture for clock and broadcast distribution using optical interconnect components, such as vertical cavity surface emitting lasers (VCSEL) and pin photodiodes with benefits of diffractive optical elements (DOE) fan-out. A two-bit-large bus for broadcast or clock distribution demonstration is presented using collective wiring technologies and MCM hybridization process in a standard BGA package. Diffractive optical elements allow one to four distribution scene through an optical plate. Specific laser drivers for VCSELs and photodiode receiver are realized in complete CMOS 0.6 μm transmitter and receiver chips.     

Optical interconnects for neural and reconfigurable VLSIarchitectures

The increasing transistor density in very large-scale integrated (VLSI) circuits and the limited pin member in the off-chip communication lead to a situation described as interconnect crisis in micro-electronics. Optoelectronic VLSI (OE-VLSI) circuits using short-distance optical interconnects and optoelectronic devices like microlaser, modulator, and detector arrays for optical off-chip sending and receiving offer a technology to overcome this crisis. However, in order to exploit efficiently the potential of thousands of optical off-chip interconnects, an appropriate VLSI architecture is required. We show for the example of neural and reconfigurable VLSI architectures that fine-grain architectures fulfill these requirements. An OE-VLSI circuit realization based on multiple quantum-well modulators functioning as two-dimensional (2-D) optical input/output (I/O) interface for the chip is presented. Due to the parallel optical interface, and improvement of two to three orders of magnitude in the throughput performance is possible compared to all-electronic solutions. For the optical interconnects, a planar-integrated free-space optical system has been designed leading to an optical multichip module. Such a system has been fabricated and experimentally characterized. Furthermore, we designed an manufactured fiber arrays, which will be the core element for a convenient test station for the 2-D optoelectronic I/O interface of OE-VLSI circuits     

Power minimization and technology comparisons for digitalfree-space optoelectronic interconnections

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSELs) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bit-rate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSELs and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 μm down to 0.1 μm brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 μm CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm² can be achieved in an optimized free-space optical interconnect system using either VCSELs or MQW modulators as its transmitters     

Fully Integrated Single Photon Avalanche Diode Detector in Standard CMOS 0.18- $mu$m Technology

Avalanche photodiodes (APDs) operating in Geiger mode can detect weak optical signals at high speed. The implementation of APD systems in a CMOS technology makes it possible to integrate the photodetector and its peripheral circuits on the same chip. In this paper, we have fabricated APDs of different sizes and their driving circuits in a commercial 0.18-mum CMOS technology. The APDs are theoretically analyzed, measured, and the results are interpreted. Excellent breakdown performance is measured for the 10 and 20 m APDs at 10.2 V. The APD system is compared to the previous implementations in standard CMOS. Our APD has a 5.5% peak probability of detection of a photon at an excess bias of 2 V, and a 30 ns dead time, which is better than the previously reported results.     

InGaAs/InP盖革模式雪崩焦平面阵列的研制

设计制作了一种由InGaAs/InP雪崩光电二极管阵列与时间计数型CMOS读出电路组成的8×8阵列规格盖革模式雪崩焦平面阵列(GM APD FPA).雪崩光电二极管采用SAGCM结构,在盖革模式下工作具有单光子探测灵敏度;时间计数型CMOS读出电路在每个单元获取光子飞行时间,实现纳秒级的时间分辨率,并完成雪崩淬灭功能.测试结果表明,倒装混合集成的GM APD FPA器件暗计数率(DCR)均值为32.5 kHz,单光子探测效率(PDE)均值为19.5％,单元时间抖动为465 ps,实现了光脉冲时间信息的探测,验证了盖革模式雪崩焦平面阵列技术及其在三维成像中应用的可行性.     

Thermal resistance of VCSELs bonded to integrated circuits

The thermal resistance of vertical-cavity surface-emitting lasers (VCSELs) flip chip bonded to GaAs substrates and CMOS integrated circuits has been measured. The measurements on GaAs show that if the bonding is done properly, the bonding does not add significantly to the thermal resistance. However, the SiO₂ under the CMOS bonding pad can double the thermal resistance unless measures are taken to improve the thermal conductance of these layers. Finite element simulations indicate that the thermal resistance of bonded VCSELs increases rapidly as the solder bond size and the aperture size decrease below ~10 μm     

基于HV-CMOS工艺集成PIN光敏元的CMOS传感器设计

PIN光电二极管相对于pn结型光电二极管具有结电容小、量子效率高等优点,但采用标准低压CMOS(LV-CMOS)工艺研制的CMOS传感器只能实现基于n阱/p衬底的pn结光敏元与片上电路的集成,高压CMOS(HV-CMOS)工艺的发展为CMOS电路与PIN光敏元列阵的单片集成提供了可能。基于HV-CMOS工艺设计了一种集成PIN光敏元列阵的CMOS传感器,并对器件的光电响应进行了测试评估。结果表明,集成PIN光敏元的CMOS传感器具有更高的像素增益和量子效率,而暗电流、输出摆幅、线性度等特性保持良好。在500~900nm宽波段范围内,器件的量子效率均达到80%以上,在950nm附近的量子效率达到25%,优于采用其他工艺制作的CMOS传感器。     

A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver IC

Source-synchronous double-data-rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to double communication bandwidth. This paper describes the design of a parallel optical transceiver integrated circuit (IC) that uses source-synchronous DDR optical signaling. On the transmit side, two 8-b electrical inputs are multiplexed, encoded, and sent over two high-speed optical links. On the receive side, the procedure is reversed to produce two 8-b electrical outputs. The proposed IC integrates analog vertical-cavity surface-emitting lasers (VCSELs), drivers and optical receivers with digital DDR multiplexing, serialization, and deserialization circuits. It was fabricated in a 0.5-$mu$m silicon-on-sapphire (SOS) complementary metal–oxide–semiconductor (CMOS) process. Linear arrays of quad VCSELs and photodetectors were attached to the proposed transceiver IC using flip-chip bonding. A free-space optical link system was constructed to demonstrate correct IC functionality. The test results show successful transceiver operation at a data rate of 500 Mb/s with a 250-MHz DDR clock, achieving a gigabit of aggregate bandwidth. While the proposed DDR scheme is well suited for low-skew fiber-ribbon, free-space, and waveguide optical links, it can also be extended to links with higher skew with the addition of skew-compensation circuitry. To the authors' knowledge, this is the first demonstration of parallel optical transceivers that use source-synchronous DDR signaling.     

A vertical-cavity surface-emitting laser appliqued to a 0.8-/spl mu/m NMOS driver

An optoelectronic integrated circuit (OEIC) composed of a vertical-cavity surface-emitting laser (VCSEL) appliqued to an NMOS drive circuit was fabricated to form an optical link from the CMOS chip. A custom NMOS circuit was designed and fabricated through the MOSIS foundry service in a standard 0.8-/spl mu/m CMOS process. InGaAs quantum-well VCSELs were grown, fabricated and tested on an n-type GaAs substrate. Next, the VCSELs underwent a substrate removal technique and were appliqued to the NMOS circuitry. The OEIC was tested at the chip level and showed an electrical to optical conversion efficiency of 1.09 mW/V. Modulation results are also discussed.     

500 /spl mu/m diameter CMOS compatible avalanche photodiodes with 500 MHz bandwidth

Novel silicon-on-insulator, large area (500 /spl mu/m diameter), CMOS avalanche photodiodes for use with plastic optical fibre are presented. Patterns have been formed on the devices to reduce junction capacitance. Measurements on the patterned devices, at 650 nm and 26 V reverse bias, revealed bandwidths of >500 MHz.     

46th Annual Device Research Conference

The following topics are dealt with: MOSFETs; random-access memories; avalanche photodiodes; optical fiber receivers; CMOS integrated circuits; high-electron mobility transistors; heterojunction bipolar transistors; MODFETs; light-emitting diodes; distributed-feedback lasers; quantum-well devices; tunneling devices; silicon-on-insulator devices; negative-resistance devices; semiconductor lasers; and power FETs. Abstracts of individual papers can be found under the relevant classification codes in this or other issues     

Low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications

State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-microm CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 microm CMOS.     

Gbit/s transmission via two-photon-absorption-inscribed optical waveguides on printed circuit boards

Optical waveguides were inscribed into a 300 mm-thick polymer layer applied onto standard printed circuit boards via two-photon-absorption. VCSELs and photodiodes embedded in this layer of ORMOCERw complemented optical interconnects for multi-Gbit/s data transmission at a wavelength of 850 nm.     

DESIGN OF SYMMETRIC TERNARY CURRENT-MODE CMOS CIRCUITS

By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.     

扩大感光动态范围的象限光电传感器的研究

介绍了一种可调整感光动态范围的象限传感器的设计。该传感器采用 0 .6微米 CMOS标准工艺制造 ,包含有 1 6× 1 6有源光电管阵列 ,相关二次采样 (CDS)电路 ,输出缓冲放大电路和数字控制电路几个主要功能模块 ,实现了象限传感器与 CMOS处理电路的兼容集成。该传感器对目标单帧传感的感光动态范围为 60 d B,通过变频二次扫描进行感光动态范围的调整后 ,传感器总的感光动态范围可以提高为 84d B。     

Sensitivity of multimode bidirectional optoelectronic modules to electrostatic discharges

Human Body Model ESD tests on two commercially available different types of wavelength division multiplexing bidirectional optoelectronic modules, intended for data transmission over multimode optical fibers at 820 and 1320 nm wavelengths, have been performed. These bidirectional modules incorporated pin diode receivers and light emitting diode in a single package. In particular, the 820 nm light emitting diodes had rather high damage threshold pulse amplitudes of about +10,000 V under forward bias and −5000 V under reverse bias conditions, and no active layer degradation has been observed. In-situ measurements of the optical transients emitted during forward bias ESD pulses enabled a damage pulse threshold detection of a LED without the need of further optoelectronic characterization. The receiver photodiodes, however, were very sensitive to reverse bias ESD pulses. The InGaAs photodiodes degraded during ESD pulses with amplitudes as low as −150 V and in the case of the Silicon photodiodes as low as −175 V.     

Application specific spectral response with CMOS compatiblephotodiodes

Several methods are presented for realizing photodiodes with independent spectral responses in a standard CMOS integrated circuit process. Only the masks, materials, and fabrication steps inherent to this standard process were used. The spectral responses of the photodiodes were controlled by (1) using the SiO₂ and polycrystalline Si as thin-film optical filters, (2) using photodiodes with different junction depths, and (3) controlling the density of the interfacial trapping centers by choosing which oxide forms the Si/SiO ₂ interface. Also presented is an example method for constructing photo-spectrometers using these spectrally-independent photodiodes. This method forms weighted sums of the photodiodes' outputs to extract spectrographic information     

Design and Characterization of CMOS/SOI Image Sensors

The design, operation, and characterization of CMOS imagers implemented using: 1) "regular" CMOS wafers with a 0.5-mum CMOS analog process; 2) "regular" CMOS wafers with a 0.35-mum CMOS analog process; and 3) silicon-on-insulator (SOI) wafers in conjunction with a 0.35-mum CMOS analog process, are discussed in this paper. The performances of the studied imagers are compared in terms of quantum efficiency, dark current, and optical bandwidth. It is found that there is strong dependence of quantum efficiency of the photodiodes on the architecture of the image sensor. The results of this paper are useful for designing and modeling CMOS/SOI image sensors