Traffic performance evaluation of an optical packet switch with multicast operation

We recently proposed a multicast-enabled optical packet switch architecture utilizing multicast modules. In this paper, we evaluate the traffic performance of our earlier proposed packet switch under a hybrid traffic model through simulations. The multicast packets are given higher priority than unicast packets so that only a small number of multicast modules are needed. The results show that the switch can achieve an acceptable packet loss probability in conjunction with a packet scheduling technique.     

Performance analysis of the ATM shuffleout switch under arbitrarynonuniform traffic patterns

Shuffleout is a blocking multistage asynchronous transfer mode (ATM) switch using shortest path routing with deflection, in which output queues are connected to all the stages. This paper describes a model for the performance evaluation of the shuffleout switch under arbitrary nonuniform traffic patterns. The analytical model that has been developed computes the load distribution on each interstage link by properly taking into account the switch inlet on which the packet has been received and the switch outlet the packet is addressing. Such a model allows the computation not only of the average load per stage but also its distribution over the different links belonging to the interstage pattern for each switch input/output pair. Different classes of nonuniform traffic patterns have been identified and for each of them the traffic performance of the switch is evaluated by thus emphasizing the evaluation of the network unfairness     

FIFO交换网络:一种保持信元次序完整性的多路径ATM交换结构

本文提出了一种新型的自选路由ＡＴＭ多路径交换结构，采用虚拟ＦＩＦＯ缓冲器技术，即能保持信元次序的完整性，又避免了螺旋式交换结构中虚拟信元引起的饱和吞吐量、延迟和信元丢失性能的下降。在均匀通信量和非均匀通信量情况下分析了它的性能，结果表明其最大可达到的饱和吞吐量为７／８，延迟和信元丢失率都比螺旋式结构小很多。同时，该系统无需内部加速，适于ＶＬＳＩ集成。     

Packet loss and delay performance of feedback and feed-forwardarrayed-waveguide gratings-based optical packet switches with WDMinputs-outputs

This paper analyzes the packet loss and delay performance of an arrayed-waveguide-grating-based (AWG) optical packet switch developed within the EPSRC-funded project WASPNET (wavelength switched packet network). Two node designs are proposed based on feedback and feed-forward strategies, using sharing among multiple wavelengths to assist in contention resolution. The feedback configuration allows packet priority routing at the expense of using a larger AWG. An analytical framework has been established to compute the packet loss probability and delay under Bernoulli traffic, justified by simulation. A packet loss probability of less than 10^-9 was obtained with a buffer depth per wavelength of 10 for a switch size of 16 inputs-outputs, four wavelengths per input at a uniform Bernoulli traffic load of 0.8 per wavelength. The mean delay is less than 0.5 timeslots at the same buffer depth per wavelength     

A buffer management scheme for the SCOQ switch under nonuniformtraffic loading

The SCOQ switch is a Batcher-banyan based high performance fast packet switch with shared concentration and output queueing, with a maximum of L(相似文献   

一种新的突发分配业务模型以及在OBS中的应用

文章提出了一种新的突发分配业务模型,给出了这种业务模型的详细定义,并应用此模型和传统的非突发分配模型对光突发交换(OBS)中的交换机构进行了性能分析和对比.计算结果表明,当交换机构扇出比F=1、突发强度B1=2时,突发分配模式下的丢包率比非突发分配模式下的丢包率增加大约一个数量级.也许该突发业务模型并不能真实地反映现实世界的业务流,但其能提供一种逼近现实世界业务流的分析方法.     

Real-time packet switching: a performance analysis

The authors model the internal structure of a packet-switching node in a real-time system and characterize the tradeoff between throughput, delay, and packet loss as a function of the buffer size, switching speed, etc. They assume a simple shared-single-path switch fabric, though the analysis can be generalized to a wider class of switch fabrics. They show that with a small number of buffers the node will provide a guaranteed delay bound for high-priority traffic, a low average delay for low-priority traffic, no loss of packets at the input and low probability of packet loss at output     

Performances of the Data Vortex switch architecture under nonuniform and bursty traffic

The Data Vortex switch architecture has been proposed as a scalable low-latency interconnection fabric for optical packet switches. This self-routed hierarchical architecture employs synchronous timing and distributed traffic-control signaling to eliminate optical buffering and to reduce the required routing logic, greatly facilitating a photonic implementation. In previous work, we have shown the efficient scalability of the architecture under uniform and random traffic conditions while maintaining high throughput and low-latency performance. This paper reports on the performance of the Data Vortex architecture under nonuniform and bursty traffic conditions. The results show that the switch architecture performs well under modest nonuniform traffic, but an excessive degree of nonuniformity will severely limit the scalability. As long as a modest degree of asymmetry between the number of input and output ports is provided, the Data Vortex switch is shown to handle very bursty traffic with little performance degradation.     

SCOQ: a fast packet switch with shared concentration and outputqueueing

A space-division, nonblocking packet switch with data concentration and output buffering is proposed. The performance of the switch is evaluated with respect to packet loss probability, the first and second moments of the equilibrium queue length and waiting time, throughput, and buffer overflow probability. Numerical results indicate that the switch exhibits very good delay-throughput performance over a wide range of input traffic. The switch compares favorably with some previously proposed switches in terms of fewer basic building elements used to attain the same degree of output buffering     

光分组交换网络的冲突解决：用光纤延迟线还是波长转换器

该文研究了光分组网络的冲突处理问题,提出了两种异于传统设计方法的交换结构。研究表明:对于非突发性业务,非简并排列方式的光纤延迟线是成本最低的解决手段;而对于突发业务,将波长转换器和延迟线结合使用是兼顾分组丢弃性能,系统体积和成本的较好策略,文中基于此给出了系统设计原则,该原则可确保系统节约大量的波长转换器和延迟线,对改善系统的整体性能十分有利。     

Round-robin selection with adaptable-size frame in a combined input-crosspoint buffered switch

As an alternative to input-buffered switches, combined input-crosspoint buffered switches relax arbitration timing and provide high-performance switching for packet switches with high-speed ports. It has been shown that these switches, with one-cell crosspoint buffer and round-robin (RR) arbitration at input and output ports, provide 100% throughput under uniform traffic. However, under admissible traffic patterns with nonuniform distributions, only weight-based selection schemes are reported to provide high throughput. We propose an RR based arbitration scheme for a combined input-crosspoint buffered packet switch that provides nearly 100% throughput for several admissible traffic patterns, including uniform and unbalanced traffic, using one-cell crosspoint buffers. The presented scheme uses adaptable-size frames, so that the frame size adapts to the traffic pattern.     

ATM交换的最佳缓存器分配

研究具有输入和输出队的ＡＴＭ交换的缓存器分配策略。文中首先建立了描述交换网络的模型，然后分析了在有限缓存容量下在输入队和输出队中分组的丢失率。分析表明总的丢失率是输入队和输出队容量的复杂函数，因而在总的缓存容量一定的情况下，必存在使丢失率最小的缓存分配方法。最后用数值结果说明了最佳的分配策略。     

Performance of a nonblocking space-division packet switch in a timevariant nonuniform traffic environment

The authors study the performance of a nonblocking space-division packet switch, given that the traffic intensities at the switch not only are nonuniform but also change as a function of time. A finite-state Markov chain is used as an underlying process to govern the time variation of traffic for the entire switch. The packet arrivals at each input form an independent Bernoulli process modulated by the underlying Markov chain. The output address of each packet is independently and randomly assigned with probability distributions, which are also modulated by the Markov chain. Provided that the traffic on each output is not dominated by individual inputs the service time of each output queue for sufficiently large switches can be characterized by an independent Markov modulated phase-type process. A matrix geometric solution for the resultant quasi-birth-death type queuing process is presented. The maximum throughput is obtained at the system saturation. The performance of the switch is numerically examined under various traffic conditions. A contention priority scheme to improve the switch performance is proposed     

The helical switch: a multipath ATM switch which preserves cellsequence

The paper presents a new cell switching architecture for ATM-based networks. The proposed helical switch is a multistage interconnection network which implements the self-routing technique with efficient buffer sharing. Although the switch may route cells along multiple paths, the connection-oriented mode required by the ATM-based network is supported. Cell sequence integrity is guaranteed by introducing a virtual helix which forces cells routed along different paths to proceed in order and fill the internal buffers uniformly. The performance of the helical switch is investigated under uniform and nonuniform traffic patterns. Unlike single-path multistage networks such as buffered banyan networks which can degrade significantly under nonuniform traffic, the helical switch is shown to be quite robust with respect to nonuniform traffic conditions     

On the combined input-crosspoint buffered switch with round-robin arbitration

Input-buffered switches have been widely considered for implementing feasible packet switches. However, their matching process may not be time-efficient for switches with high-speed ports. Buffered crossbars (BXs) are an alternative to relax timing for packet switches with high-speed ports and to provide high-performance switching. BX switches were originally considered expensive, as the memory amount required in the crosspoints (XPs) is proportional to the square of the number of ports (O(N/sup 2/)). This limitation is now less stringent with the advances on chip-fabrication techniques, and when considering small crosspoint (XP) buffer sizes. In this paper, we study a combined input-crosspoint buffered packet switch, named CIXB, with virtual output queues (VOQs) at the inputs, and arbitration based on round-robin selection. We show that the CIXB switch achieves 100% throughput under uniform traffic, and high performance under nonuniform traffic, using one-cell XP buffer size and no speedup.     

Analysis of input and output queueing for nonblocking ATM switches

A switch model for ATM networks is analyzed. Its interconnection network is internally nonblocking and is provided with dedicated input and output queues, one per switch inlet and one per switch outlet. The switch operates with an internal speed-up: more than one packet per slot can be transferred from the head-of-line positions of the input queues to each output queue by the interconnection network. Two different operation modes are considered for the interaction between input and output queues: backpressure mode and queue loss mode. The analytical model developed for the evaluation of the switch performance under random traffic assumes an infinite size for the switch, arbitrary values for input and output queue size, as well as for the speed-up factor. Switch throughput, packet delay and loss performance are evaluated and the analytical model accuracy is assessed using computer simulation results     

A TDM-based multibus packet switch

A new packet switch architecture using two sets of time-division multiplexed buses is proposed. The horizontal buses collect packets from the input links, while the vertical buses distribute the packets to the output links. The two sets of buses are connected by a set of switching elements which coordinate the connections between the horizontal buses and the vertical buses so that each vertical bus is connected to only one horizontal bus at a time. The switch has the advantages of: (1) adding input and output links without increasing the bus and I/O adaptor speed; (2) being internally unbuffered; (3) having a very simple control circuit; and (4) having 100% throughput under uniform traffic. A combined analytical-simulation method is used to obtain the packet delay and packet loss probability. Numerical results show that for satisfactory performance, the buses need to run about 30% faster than the input line rate. With this speedup, even at a utilization factor of 0.9, each input adaptor requires only 31 buffers for a packet loss rate of 10^-6. The output queue behaves essentially as an M/D/1 queue     

Packet loss in a bufferless optical WDM switch employing sharedtunable wavelength converters

We propose an architecture for a bufferless packet optical switch employing the wavelength dimension for contention resolution. The optical packet switch is equipped with tunable wavelength converters shared among the input lines. An analytical model Is proposed in order to determine the number of converters needed to satisfy prefixed packet loss probability constraints. This analytical model very accurately fits with simulations results. A sensitivity analysis of the required number of converters as a function of the main system parameters (number of input and output lines, number of wavelengths, …) and traffic parameters has been carried out. Making use of the introduced dimensioning procedure we have observed that the proposed architecture allows a saving in terms of employed number of converters with respect to the other architectures proposed in literature. Such a saving can reach about 95% of the number of converters     

Performance analysis of handover delay and buffer capacity in mobile OpenFlow‐based networks

Software‐defined networking (SDN) is a network concept that brings significant benefits for the mobile cellular operators. In an SDN‐based core network, the average service time of an OpenFlow switch is highly influenced by the total capacity and type of the output buffer, which is used for temporary storage of the incoming packets. In this work, the main goal is to model the handover delay due to the exchange of OpenFlow‐related messages in mobile SDN networks. The handover delay is defined as the overall delay experienced by the mobile node within the handover procedure, when reestablishing an ongoing session from the switch in the source eNodeB to the switch in the destination eNodeB. We propose a new analytical model, and we compare two systems with different SDN switch designs that model a continuous time Markov process by using quasi‐birth–death processes: (1) single shared buffer without priority (model SFB), used for all output ports for both control and user traffic, and (2) two isolated buffers with priority (model priority finite buffering [PFB]), one for control and the other for user plane traffic, where the control traffic is always prioritized. The two proposed systems are compared in terms of total handover delay and minimal buffer capacity needed to satisfy a certain packet error ratio imposed by the link. The mathematical modeling is verified via extensive simulations. In terms of handover delay, the results show that the model PFB outperforms the model SFB, especially for networks with high number of users and high probability of packet‐in messages. As for the buffer dimensioning analysis, for lower arrival rates, low number of users, and low probability of packet‐in messages, the model SFB has the advantage of requiring a smaller buffer size.     

Cell loss analysis and design trade-offs of nonblocking ATMswitches with nonuniform traffic

In practical ATM switch design, a proper dimensioning of buffer sizes and a cost effective selection of speed-up factor should be considered to guarantee a specified cell loss requirement for a given traffic. Although a larger speed-up factor provides better throughput for the switch, increasing the speed-up factor involves greater complexity and cost. Hence, it may not be cost effective to increase the speed-up factor for 100% throughput. Moreover, with a given buffer budget, an increase in the speed-up factor beyond a certain value only adds to the cell loss. The paper addresses design trade-offs existing between finite input/output buffer sizes and speed-up factor in a nonblocking ATM switch. Another important issue is the adverse effect on cell loss performance caused by nonuniform traffic (different traffic intensity and unevenly distributed routing). The paper analyzes cell loss performance of ATM switches with nonuniform traffic, and examines the effect of each nonuniform traffic parameter. The authors also provide an algorithm for effective buffer sharing that alleviates the performance degradation caused by traffic nonuniformity