交流信号对亚微米CMOS集成电路可靠性的影响

介绍了交流信号对亚微米CMOS集成电路可靠性的影响,重点分析了亚微米CMOS集成电路中交流应力下的热载流子效应、电迁移、栅氧化层介质击穿效应。通过与直流应力下器件可靠性的对比,分析交流信号与直流信号对亚微米CMOS集成电路可靠性影响的差异。     

深亚微米CMOS器件可靠性机理及模型

随着CMOS集成电路特征尺寸的不断缩小,特别是在其发展到深亚微米阶段之后,CMOS器件面临着负偏置温度的不稳定性、栅氧化层经时击穿、互连系统的电迁移和热载流子注入等可靠性问题。重点对近年来研究得到的深亚微米CMOS器件可靠性机理及其可靠性模型进行了总结。     

VLSI CMOS模拟集成电路可靠性仿真设计技术

随着超大规模CMOS模拟集成电路工艺技术进入纳米阶段,模拟集成电路面临着日益严峻的可靠性挑战,可靠性仿真设计技术已经成为提升电路固有可靠性的重要途径.对现有的模拟集成电路可靠性仿真设计的文献资料进行了总结,探讨了集成电路可靠性仿真分析的高效方法,这些方法能够帮助电路设计师对电路进行分析,并找出其中的薄弱环节.介绍了典型的更具适应性和自愈能力的模拟集成电路设计技术.     

毫米波CMOS集成电路的现状与趋势

随着深亚微米和纳米CMOS工艺的成熟,设计和实现低成本的毫米波CMOS集成电路已成为可能.简述了毫米波CMOS技术的发展现状,介绍了毫米波CMOS集成电路的关键技术,即晶体管建模和传输线建模,并给出了毫米波CMOS电路的最新进展和发展趋势.     

CMOS器件及其结构缺陷的显微红外发光现象研究

CMOS器件结构依靠其较低的功耗和高集成度而广泛应用于集成电路中,它在正常工作和发生失效时均存在微弱的显微红外发光现象。对CMOS结构的显微红外发光现象产生机制进行了研究和实际观察,将对深入了解CMOS器件中各种红外发光效应和分析其可靠性具有实际意义。     

可靠性仿真在机载雷达中的应用与分析

文中描述了可靠性仿真技术与传统可靠性设计、分析和试验方法的区别及优缺点;以一种机载雷达为例,利用计算机辅助设计数字样机,结合耐振动设计、热设计信息,建立产品的有限元分析、计算流体动力学数字样机,并通过可靠性建模与仿真分析,查找出设计中的薄弱环节,指明潜在故障的位置和原因,为产品设计改进提供了支撑依据。     

射频功率放大器互连可靠性的神经网络建模研究北大核心CSCD

以一个GaAs单片微波集成电路功率放大器为例进行了三维互连可靠性建模与分析,提出将人工神经网络技术与传统的有限元分析方法相结合来实现电路互连可靠性的快速预测,有效地克服了有限元分析耗时耗资源的缺点。通过训练从ANSYS得到的可靠性数据,人工神经网络技术可以快速构建该模型的输入输出关系,进一步分析建模得到的互连可靠性数据库,进而得到该功率放大器可靠性最佳的晶体管尺寸和工作条件,这为集成电路的互连可靠性设计和分析提供了重要指导。     

基于40nm CMOS工艺电路的NBTI退化表征方法

负偏压温度不稳定性(NBTI)退化是制约纳米级集成电路性能及寿命的主导因素之一,基于40 nm CMOS工艺对NBTI模型、模型提参及可靠性仿真展开研究。首先对不同应力条件下PMOS晶体管NBTI退化特性进行测试、建模及模型参数提取,然后建立了基于NBTI效应的VerilogA等效受控电压源,并嵌入Spectre^TM仿真库中,并将此受控电压源引入反相器及环形振荡器模块电路中进行可靠性仿真分析,可有效反映NBTI退化对电路性能的影响。提出了一套完整可行的电路NBTI可靠性预测方法,包括NBTI模型、模型参数提取、VerilogA可靠性模型描述以及电路级可靠性仿真分析,可为纳米级高性能、高可靠性集成电路设计提供有效参考。     

高频和高压电子元器件的装配质量控制措施

主要介绍高频微波器件如隔离器、环行器、高压器件、触发管、对静电敏感的CMOS集成电路及SMT型片式电阻器装配工艺控制措施，以保证装配质量，提高整机的可靠性。     

SCR器件在CMOS静电保护电路中的应用

静电放电(ESD)对CMOS电路的可靠性构成了很大威胁。随着CMOS电路集成度的不断提高，其对ESD保护的要求也更加严格。针对近年来SCR器件更加广泛地被采用到CMOS静电保护电路中的情况，文章总结了SCR保护电路发展过程中各种电路的工作机理。旨在为集成电路设计人员提供ESD保护方面的设计思路以及努力方向。     

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods.     

Advanced integrated-circuit reliability simulation includingdynamic stress effects

A systematic approach to predict semiconductor degradation effects using reliability simulation is described. The DC degradation monitor is first extracted during transient circuit simulation. An AC degradation factor is then used to determine circuit performance degradation. By using these techniques on the design of CMOS components, proper long-term reliability can be achieved for high-speed circuits. Experimental results on digital circuits using an industrial submicrometer technology demonstrate the effectiveness of this approach in reliable VLSI circuit design. Results on two-input NAND gates, DRAM precharging circuit, and SRAM control circuits are presented     

CMOS工艺中抗闩锁技术的研究

伴随着CMOS工艺技术的发展,CMOS电路已经成为VLSI制造中的主流,而CMOS器件特征尺寸的快速缩小和CMOS电路的广泛应用,使得CMOS电路中的latch-up效应引起的可靠性问题也越来越受到大家的重视。阐述了CMOS工艺中闩锁的概念、原理及其给电路的可靠性带来的严重后果,深入分析了产生闩锁效应的条件、触发方式,并针对所分析的闩锁原因从版图设计、工艺改良、电路应用三个方面提出了一些防闩锁的优化措施,以满足和提高CMOS电路的可靠性要求。     

Fault model for sub-micron CMOS ULSI circuits reliability assessment

A new fault model, based on the general Percolation theory applied to long-channel CMOS VLSI circuits, has been recently introduced. It was shown that a reliability risk appears only when process-related defects create a pattern independent current path in standby mode. An acceptable reliability risk defines pass/fail criteria. A screening technique, based on this model, presents a strong correlation between rejected devices and Early Failure Rate.In this paper, the general Percolation approach was applied to short-channel CMOS VLSI circuits. Unlike long-channel CMOS VLSI, defect-free short-channel CMOS VLSI circuits inherently have a pattern-independent standby current. It results from a short-channel MOSFET current in the off state. In this case, the defect-related component of this current might be released only by means of a multi parameter fail criterion. Experimental results that confirm this conclusion are presented and discussed. The Reliability Risk assessment technique employing this model shows a strong correlation between rejected devices and long term reliability for 32-bit 0.35 μM CMOS microprocessors.     

一种新型的集成电路片上CMOS温度传感器

介绍了一种可以用于片上温度监控的CMOS温度传感器,该传感器具有面积小、功耗低、精度高、易于实现等优点,可以比较容易地集成到芯片上实现温度监测功能.     

MOSFET衬底电流模型及参数提取

在短沟道ＭＯＳＦＥＴ器件物理的基础上,导出了其衬底电流解析模型,并通过实验进行了模型参数提取。模型输出与短沟ＭＯＳＦＥＴ实测结果比较接近,可应用于ＶＬＳＩ／ＵＬＳＩ可靠性模拟与监测研究和亚微米ＣＭＯＳ电路设计。     

A graph based approach for reliability analysis of nano-scale VLSI logic circuits

Advances in nano-electronics VLSI manufacturing technology and the rapid downscaling of the size of logic circuits have made them more prone to errors. This has led to the need for fast circuit reliability evaluation of large logic circuits. In this paper a new method for reliability analysis of VLSI logic circuits based on a modified form of Mason’s rule is proposed. Utilizing matrix sparsity significantly increases the speed and reduces the required memory of the proposed approach. In addition, an approach is introduced to mitigate the effect of reconvergent paths. Simulation results indicate that the proposed method is scalable and runs 4× faster than previously proposed schemes.     

Impact of gate induced drain leakage on overall leakage ofsubmicrometer CMOS VLSI circuits

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield     

Performance-Oriented Parameter Dimension Reduction of VLSI Circuits

To account for the growing process variability in modern VLSI technologies, circuit models parameterized in a multitude of parametric variations are becoming increasingly indispensable in robust circuit design. However, the high parameter dimensionality can introduce significant complexity and may even render variation-aware performance analysis and optimization completely intractable. We present a performance-oriented parameter dimension reduction framework to reduce the modeling complexity associated with high parameter dimensionality. Our framework has a theoretically sound statistical basis, namely, reduced rank regression (RRR) and its various extensions that we have introduced for more practical VLSI circuit modeling. For a variety of VLSI circuits including interconnects and CMOS digital circuits, it is shown that this parameter reduction framework can provide more than one order of magnitude reduction in parameter dimensionality. Such parameter reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more importantly, highly efficient parameterized sub-circuit models that are instrumental in tackling the complexity of variation-tolerance VLSI system design.